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Jinming Lu
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2020 – today
- 2024
- [j9]Jinming Lu
, Hui Wang
WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 634-645 (2024) - 2023
- [j8]Jinming Lu
Cathode Shape Design for Steady-State Electrochemical Machining. Algorithms 16(2): 67 (2023) - [j7]Jinming Lu
ETA: An Efficient Training Accelerator for DNNs Based on Hardware-Algorithm Co-Optimization. IEEE Trans. Neural Networks Learn. Syst. 34(10): 7660-7674 (2023) - [j6]Haikuo Shao
An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1788-1801 (2023) - [c10]Mingming Zhang, Liu Jie, Jinming Lu:
Data Analysis for Machine Sound Detection: Challenges, Methods, and Future Trends. CISP-BMEI 2023: 1-5 - [c9]Hui Wang, Jinming Lu, Jun Lin, Zhongfeng Wang:
An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd. ISVLSI 2023: 1-6 - 2022
- [j5]Jinming Lu
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration. IEEE Trans. Very Large Scale Integr. Syst. 30(8): 1034-1046 (2022) - [c8]Mingyang Xu, Jinming Lu, Zhongfeng Wang, Jun Lin:
An Efficient CNN Training Accelerator Leveraging Transposable Block Sparsity. AICAS 2022: 230-233 - [c7]Jian Huang, Jinming Lu, Zhongfeng Wang:
An Efficient Hardware Architecture for DNN Training by Exploiting Triple Sparsity. ISCAS 2022: 2802-2805 - 2021
- [j4]Jinming Lu
Evaluations on Deep Neural Networks Training Using Posit Number System. IEEE Trans. Computers 70(2): 174-187 (2021) - [c6]Tongtong Yin, Wendong Mao, Jinming Lu, Zhongfeng Wang:
A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA. ISVLSI 2021: 144-149 - [c5]Haikuo Shao
An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training. ISVLSI 2021: 254-259 - 2020
- [c4]Chao Ni
LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks. APCCAS 2020: 201-204 - [c3]Jinming Lu
A Reconfigurable DNN Training Accelerator on FPGA. SiPS 2020: 1-6
2010 – 2019
- 2019
- [j3]Siyuan Lu
A Hardware-Oriented and Memory-Efficient Method for CTC Decoding. IEEE Access 7: 120681-120694 (2019) - [j2]Meiqi Wang
E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 280-291 (2019) - [c2]Siyuan Lu, Jinming Lu
A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding. SiPS 2019: 352-357 - [c1]Jinming Lu
Training Deep Neural Networks Using Posit Number System. SoCC 2019: 62-67 - [i2]Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang:
A Hardware-Oriented and Memory-Efficient Method for CTC Decoding. CoRR abs/1905.03175 (2019) - [i1]Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, Li Du:
Training Deep Neural Networks Using Posit Number System. CoRR abs/1909.03831 (2019) - 2018
- [j1]Jianwei Feng
Quantitative Prediction of 3-D Multiple Parameters of Tectonic Fractures in Tight Sandstone Reservoirs Based on Geomechanical Method. IEEE Access 6: 39096-39116 (2018)
Coauthor Index
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last updated on 2024-09-26 01:01 CEST by the dblp team
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