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Sasindu Wijeratne
Person information
- affiliation: University of Southern California, CA, USA
- affiliation (former): University of Moratuwa, Sri Lanka
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2020 – today
- 2024
- [c14]Sasindu Wijeratne
, Rajgopal Kannan
Sparse MTTKRP Acceleration for Tensor Decomposition on GPU. CF 2024 - [i12]Sasindu Wijeratne, Bingyi Zhang, Rajgopal Kannan, Viktor K. Prasanna, Carl E. Busart:
PAHD: Perception-Action based Human Decision Making using Explainable Graph Neural Networks on SAR Images. CoRR abs/2401.02687 (2024) - [i11]Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna:
Sparse MTTKRP Acceleration for Tensor Decomposition on GPU. CoRR abs/2405.08470 (2024) - 2023
- [c13]Sasindu Wijeratne
Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA. FPGA 2023: 259-269 - [c12]Paul Chen, Pavan Manjunath, Sasindu Wijeratne, Bingyi Zhang, Viktor K. Prasanna:
Exploiting On-Chip Heterogeneity of Versal Architecture for GNN Inference Acceleration. FPL 2023: 219-227 - [c11]Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna:
Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU. SBAC-PAD 2023: 23-33 - [i10]Bingyi Zhang, Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna, Carl E. Busart:
Graph Neural Network for Accurate and Low-complexity SAR ATR. CoRR abs/2305.07119 (2023) - [i9]Paul Chen, Pavan Manjunath, Sasindu Wijeratne, Bingyi Zhang, Viktor K. Prasanna:
Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration. CoRR abs/2308.02749 (2023) - [i8]Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna:
Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU. CoRR abs/2309.09131 (2023) - 2022
- [c10]Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna:
Towards Programmable Memory Controller for Tensor Decomposition. DATA 2022: 468-475 - [c9]Sasindu Wijeratne, Akhilesh R. Jaiswal, Ajey P. Jacob, Bingyi Zhang, Viktor K. Prasanna:
Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA. HPEC 2022: 1-7 - [c8]Bingyi Zhang, Akhilesh R. Jaiswal, Clynn Mathew, Ravi Teja Lakkireddy, Ajey P. Jacob, Sasindu Wijeratne, Viktor K. Prasanna:
Modeling the Energy Efficiency of GEMM using Optical Random Access Memory. HPEC 2022: 1-7 - [c7]Tian Ye, Sanmukh R. Kuppannagari, César A. F. De Rose, Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna:
Estimating the Impact of Communication Schemes for Distributed Graph Processing. ISPDC 2022: 49-56 - [i7]Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna:
Towards Programmable Memory Controller for Tensor Decomposition. CoRR abs/2207.08298 (2022) - [i6]Sasindu Wijeratne, Akhilesh R. Jaiswal, Ajey P. Jacob, Bingyi Zhang, Viktor K. Prasanna:
Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA. CoRR abs/2208.10593 (2022) - 2021
- [c6]Sasindu Wijeratne, Sanket Pattnaik, Zhiyu Chen, Rajgopal Kannan, Viktor K. Prasanna:
Programmable FPGA-based Memory Controller. HOTI 2021: 43-51 - [c5]Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna:
Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA. HPEC 2021: 1-7 - [i5]Ruizhi Zhang, Sasindu Wijeratne, Yang Yang, Sanmukh R. Kuppannagari, Viktor K. Prasanna:
A High Throughput Parallel Hash Table on FPGA using XOR-based Memory. CoRR abs/2108.03390 (2021) - [i4]Sasindu Wijeratne, Sanket Pattnaik, Zhiyu Chen, Rajgopal Kannan, Viktor K. Prasanna:
Programmable FPGA-based Memory Controller. CoRR abs/2108.09601 (2021) - [i3]Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual:
Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks. CoRR abs/2109.03040 (2021) - [i2]Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna:
Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA. CoRR abs/2109.08874 (2021) - 2020
- [c4]Ruizhi Zhang, Sasindu Wijeratne, Yang Yang, Sanmukh R. Kuppannagari
A High Throughput Parallel Hash Table on FPGA using XOR-based Memory. HPEC 2020: 1-7
2010 – 2019
- 2019
- [c3]Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual:
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. FPGA 2019: 117 - [i1]Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual:
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. CoRR abs/1910.13683 (2019) - 2018
- [c2]Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual:
Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks. ASAP 2018: 1-7 - 2017
- [c1]Rishan Senanayake, Namitha Liyanage
High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension. ASAP 2017: 164-169
Coauthor Index
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last updated on 2024-10-07 21:13 CEST by the dblp team
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