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Reza Navid
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2020 – today
- 2024
- [c5]Dong-Myung Choi, Yikui Dong, Roan Nicholson, Frank Liu, Wenyan Jia, Vadim Levin, Mike He, Sameer Pradhan, Jieqiong Du, Michael De Vita, Amanda Tran, Reza Navid, Sitaraman Iyer, Rui Song:
A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology. VLSI Technology and Circuits 2024: 1-2
2010 – 2019
- 2015
- [j6]Mohammad Hekmat, Farshid Aryanfar, Jason Wei, Vijay P. Gadde, Reza Navid:
A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators. IEEE J. Solid State Circuits 50(2): 490-502 (2015) - [j5]Reza Navid, E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble:
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology. IEEE J. Solid State Circuits 50(4): 814-827 (2015) - 2014
- [c4]E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Reza Navid, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble:
A 40-Gb/s serial link transceiver in 28-nm CMOS technology. VLSIC 2014: 1-2 - [c3]Masum Hossain, E-Hung Chen, Reza Navid, Brian S. Leibowitz, Chuen-Huei Adam Chou, Simon Li, Myeong-Jae Park, Jihong Ren, Barry Daly, Bruce Su, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble:
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering. VLSIC 2014: 1-2 - 2010
- [j4]Reza Navid, Thomas H. Lee, Robert W. Dutton:
Circuit-Based Characterization of Device Noise Using Phase Noise Data. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(6): 1265-1272 (2010)
2000 – 2009
- 2009
- [j3]Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Yohan Frans, Brian S. Leibowitz, Nhat Nguyen, T. J. Chin, Kambiz Kaviani, Jie Shen, Xudong Shi, Wendemagegnehu T. Beyene, Simon Li, Reza Navid, Marko Aleksic, Fred S. Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fariborz Assaderaghi:
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface. IEEE J. Solid State Circuits 44(4): 1235-1247 (2009) - 2007
- [c2]Reza Navid, Thomas H. Lee, Robert W. Dutton:
A Circuit-Based Noise Parameter Extraction Technique for MOSFETs. ISCAS 2007: 3347-3350 - 2005
- [j2]Reza Navid, Thomas H. Lee, Robert W. Dutton:
Minimum achievable phase noise of RC oscillators. IEEE J. Solid State Circuits 40(3): 630-637 (2005) - [j1]Reza Navid, Thomas H. Lee, Robert W. Dutton:
An analytical formulation of phase noise of signals with Gaussian-distributed jitter. IEEE Trans. Circuits Syst. II Express Briefs 52-II(3): 149-153 (2005) - 2003
- [c1]Reza Navid, Thomas H. Lee, Robert W. Dutton:
Lumped, inductorless oscillators: how far can they go? [phase noise reduction limit]. CICC 2003: 543-546
Coauthor Index
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