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Takahiro Irita
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2020 – today
- 2022
- [j10]Katsushige Matsubara
, Hanno Lieske
A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control. IEEE J. Solid State Circuits 57(1): 115-126 (2022) - 2021
- [c15]Katsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Kazuaki Terashima, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei:
4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control. ISSCC 2021: 56-58
2010 – 2019
- 2017
- [j9]Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori:
A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2878-2887 (2017) - [j8]Shinichi Shibahara
A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard. IEEE J. Solid State Circuits 52(1): 77-88 (2017) - 2016
- [c14]Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori:
4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems. ISSCC 2016: 78-79 - [c13]Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji, Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita:
4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability. ISSCC 2016: 80-81 - 2013
- [j7]Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Takeshi Kataoka, Toshihiro Hattori:
Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor. IEEE Micro 33(6): 26-36 (2013) - [c12]Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Takeshi Kataoka, Toshihiro Hattori:
A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor. ISSCC 2013: 156-157 - 2010
- [j6]Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori:
A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits. IEEE J. Solid State Circuits 45(1): 59-68 (2010)
2000 – 2009
- 2009
- [j5]Masayuki Ito, Kenichi Nitta, Koji Ohno, Masahito Saigusa, Masaki Nishida, Shinichi Yoshioka, Takahiro Irita, Takao Koike, Tatsuya Kamei, Teruyoshi Komuro, Toshihiro Hattori, Yasuhiro Arai, Yukio Kodama:
A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU. IEEE J. Solid State Circuits 44(1): 83-89 (2009) - [c11]Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka:
A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management. ASP-DAC 2009: 535-539 - [c10]Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori:
A 342mW mobile application processor with full-HD multi-standard video codec. ISSCC 2009: 158-159 - 2008
- [c9]Masao Naruse, Tatsuya Kamei, Toshihiro Hattori, Takahiro Irita, Kenichi Nitta, Takao Koike, Shinichi Yoshioka, Koji Ohno, Masahito Saigusa, Minoru Sakata, Yukio Kodama, Yuji Arai, Teruyoshi Komuro:
A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU. ISSCC 2008: 260-261 - 2007
- [j4]Tetsuya Yamada, Naohiko Irie, Takanobu Tsunoda, Takahiro Irita, Kenji Kitagawa, Ryohei Yoshida, Keisuke Toyama, Motoaki Satoyama:
A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core. IEICE Trans. Electron. 90-C(2): 523-530 (2007) - [j3]Yusuke Kanno, Hiroyuki Mizuno
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. IEEE J. Solid State Circuits 42(1): 74-83 (2007) - [j2]Yusuke Kanno, Yuki Kondoh, Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu, Shigenobu Komatsu, Hiroyuki Mizuno
In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution. IEEE J. Solid State Circuits 42(4): 784-789 (2007) - [c8]Masayuki Ito, Toshihiro Hattori, Takahiro Irita, Ken Tatezawa, Fumihito Tanaka, Kenji Hirose, Shinichi Yoshioka, Koji Ohno, Reiko Tsuchihashi, Minoru Sakata, Masayuki Yamamoto, Yuji Aral:
A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS. ISSCC 2007: 274-602 - 2006
- [c7]Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno:
Hierarchical power distribution and power management scheme for a single chip mobile processor. DAC 2006: 292-295 - [c6]Masayuki Ito, Takahiro Irita, Eiji Yamamoto, Kunihiko Nishiyama, Takao Koike, Yoshihiko Tsuchihashi, Hiroyuki Asano, Hiroshi Yagi, Saneaki Tamaki, Ken Tatezawa, Toshihiro Hattori, Shinichi Yoshioka, Koji Ohno:
SH-MobileG1: A single-chip application and dual-mode baseband processor. Hot Chips Symposium 2006: 1-24 - [c5]Yusuke Kanno, Hiroyuki Mizuno
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. ISSCC 2006: 2200-2209 - [c4]Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno:
A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor. ISSCC 2006: 2210-2219 - 2005
- [c3]Shoichi Kamae, Takahiro Irita, Akifumi Tsukimori, Saneaki Tarnaki, Toshihiro Hattori, Shinichi Yoshioka:
SH-mobile - low power application processor for cellular [3G cellular phones]. ISCAS (5) 2005: 5349-5352
1990 – 1999
- 1999
- [j1]Takahiro Irita, Takayuki Ogura, Minoru Fujishima, Koichiro Hoh:
Microprocessor architecture utilizing redundant-binary operation. Syst. Comput. Jpn. 30(13): 106-115 (1999) - 1998
- [c2]Teppei Tsujita, Takahiro Irita, Minoru Fujishima, Koichiro Hoh:
Self-oscillating chaos generator using CMOS multivibrator. KES (1) 1998: 213-217 - [c1]Koichiro Hoh, Takahiro Irita, Teppei Tsujita, Minoru Fujishima:
Generation of chaos with simple sets of semiconductor devices. KES (3) 1998: 250-259
Coauthor Index
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