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Bahar Asgari
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2020 – today
- 2024
- [c20]Ubaid Bakhtiar, Helya Hosseini, Bahar Asgari:
Acamar: A Dynamically Reconfigurable Scientific Computing Accelerator for Robust Convergence and Minimal Resource Underutilization. MICRO 2024: 1601-1616 - [i9]Sanjali Yadav, Bahar Asgari:
Misam: Using ML in Dataflow Selection of Sparse-Sparse Matrix Multiplication. CoRR abs/2406.10166 (2024) - [i8]Donghyeon Joo, Ramyad Hadidi, Soheil Feizi, Bahar Asgari:
Endor: Hardware-Friendly Sparse Format for Offloaded LLM Inference. CoRR abs/2406.11674 (2024) - [i7]Armin Gerami, Bahar Asgari:
GUST: Graph Edge-Coloring Utilization for Accelerating Sparse Matrix Vector Multiplication. CoRR abs/2410.09106 (2024) - 2023
- [c19]Dheeraj Ramchandani, Bahar Asgari
, Hyesoon Kim:
Spica: Exploring FPGA Optimizations to Enable an Efficient SpMV Implementation for Computations at Edge. EDGE 2023: 36-42 - [c18]Ramyad Hadidi, Jiashen Cao, Bahar Asgari, Hyesoon Kim:
Creating Robust Deep Neural Networks with Coded Distributed Computing for IoT. EDGE 2023: 126-132 - [c17]Ramyad Hadidi, Nima Shoghi Ghaleshahi, Bahar Asgari, Hyesoon Kim:
Context-Aware Task Handling in Resource-Constrained Robots with Virtualization. EDGE 2023: 255-261 - [c16]Foroozan Karimzadeh, Mohsen Imani, Bahar Asgari, Ningyuan Cao, Yingyan Lin, Yan Fang:
Memory-Based Computing for Energy-Efficient AI: Grand Challenges. VLSI-SoC 2023: 1-8 - 2022
- [c15]Bahar Asgari
Maia: Matrix Inversion Acceleration Near Memory. FPL 2022: 277-281 - 2021
- [b1]Bahar Asgari:
Efficiently Accelerating Sparse Problems by Enabling Stream Accesses to Memory using Hardware/Software Techniques. Georgia Institute of Technology, Atlanta, GA, USA, 2021 - [j5]Bahar Asgari
Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware. IEEE Trans. Computers 70(4): 524-538 (2021) - [j4]Bahar Asgari
MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System. J. Signal Process. Syst. 93(6): 659-675 (2021) - [c14]Ramyad Hadidi
Quantifying the design-space tradeoffs in autonomous drones. ASPLOS 2021: 661-673 - [c13]Bahar Asgari
FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction. HPCA 2021: 908-920 - [c12]Bahar Asgari
Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads. IISWC 2021: 1-12 - [i6]Ramyad Hadidi, Nima Shoghi Ghaleshahi, Bahar Asgari, Hyesoon Kim:
Context-Aware Task Handling in Resource-Constrained Robots with Virtualization. CoRR abs/2104.04563 (2021) - 2020
- [c11]Bahar Asgari
PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse Algebra. DAC 2020: 1-6 - [c10]Bahar Asgari, Ramyad Hadidi
ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to Memory. DATE 2020: 318-321 - [c9]Bahar Asgari, Ramyad Hadidi, Hyesoon Kim:
Proposing a Fast and Scalable Systolic Array for Matrix Multiplication. FCCM 2020: 204 - [c8]Bahar Asgari
ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator. HPCA 2020: 249-260 - [c7]Bahar Asgari
MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic Architecture. ICCD 2020: 130-137 - [i5]Ramyad Hadidi, Bahar Asgari, Jiashen Cao, Younmin Bae, Hyojong Kim, Michael S. Ryoo, Hyesoon Kim:
Edge-Tailored Perception: Fast Inferencing in-the-Edge with Efficient Model Distribution. CoRR abs/2003.06464 (2020) - [i4]Bahar Asgari, Ramyad Hadidi, Joshua Dierberger, Charlotte Steinichen, Hyesoon Kim:
Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads. CoRR abs/2011.10932 (2020)
2010 – 2019
- 2019
- [j3]Bahar Asgari
ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays. IEEE Micro 39(5): 46-54 (2019) - [c6]Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili:
LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays. DAC 2019: 233 - [c5]Prashant J. Nair, Bahar Asgari
SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM. DSN 2019: 388-400 - [c4]Younmin Bae, Ramyad Hadidi, Bahar Asgari, Jiashen Cao, Hyesoon Kim:
Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNs. FPL 2019: 421 - [c3]Ramyad Hadidi
Characterizing the Deployment of Deep Neural Networks on Commercial Edge Devices. IISWC 2019: 35-48 - 2018
- [c2]Ramyad Hadidi
Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube. ISPASS 2018: 99-108 - [i3]Bahar Asgari, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems. CoRR abs/1803.06068 (2018) - 2017
- [j2]Ramin Rajaei, Bahar Asgari, Mahmoud Tabandeh, Mahdi Fazeli
Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology. Turkish J. Electr. Eng. Comput. Sci. 25: 1035-1047 (2017) - [j1]Bahar Asgari, Mahdi Fazeli
Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file. IET Comput. Digit. Tech. 11(1): 1-7 (2017) - [c1]Ramyad Hadidi
Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube. IISWC 2017: 66-75 - [i2]Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar, Saibal Mukhopadhyay, Sudhakar Yalamanchili, Hyesoon Kim:
Demystifying the Characteristics of 3D-Stacked Memories: A Case Study for Hybrid Memory Cube. CoRR abs/1706.02725 (2017) - [i1]Ramyad Hadidi, Bahar Asgari, Jeffrey S. Young, Burhan Ahmad Mudassar, Kartikay Garg, Tushar Krishna, Hyesoon Kim:
Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube. CoRR abs/1707.05399 (2017)
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