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Ckristian Duran
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2020 – today
- 2024
- [c14]Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Khai-Duy Nguyen, Tetsuya Iizuka, Trong-Thuc Hoang, Cong-Kha Pham
:
A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology. ISCAS 2024: 1-5 - [i1]Nanako Kimura, Ckristian Duran, Zolboo Byambadorj, Ryosho Nakane, Tetsuya Iizuka:
Hardware-Friendly Implementation of Physical Reservoir Computing with CMOS-based Time-domain Analog Spiking Neurons. CoRR abs/2409.11612 (2024) - 2023
- [c13]Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Tuan-Kiet Dang
In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology. ISCAS 2023: 1-5 - 2022
- [j12]Ronaldo Serrano
A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse. IEEE Access 10: 41852-41862 (2022) - [j11]Trong-Thuc Hoang
Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling. IEEE Access 10: 46014-46027 (2022) - [j10]Ronaldo Serrano
A Unified NVRAM and TRNG in Standard CMOS Technology. IEEE Access 10: 79213-79221 (2022) - [j9]Ronaldo Serrano
ChaCha20-Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3. Cryptogr. 6(2): 30 (2022) - [j8]Ronaldo Serrano
A Unified PUF and Crypto Core Exploiting the Metastability in Latches. Future Internet 14(10): 298 (2022) - [j7]Ckristian Duran
A 10pJ/bit 256b AES-SoC Exploiting Memory Access Acceleration. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1612-1616 (2022) - [j6]Marco Sarmiento
Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 69(5): 2438-2442 (2022) - [c12]Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Trong-Thuc Hoang, Cong-Kha Pham:
A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore. ISOCC 2022: 79-80 - 2021
- [j5]Ronaldo Serrano
A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse. IEEE Access 9: 105748-105755 (2021) - [j4]Marco Sarmiento
A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3182-3186 (2021) - [c11]Trong-Thuc Hoang, Ckristian Duran, Ronaldo Serrano, Marco Sarmiento, Khai-Duy Nguyen, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture. HCS 2021: 1-16 - [c10]Ckristian Duran, Héctor Gómez, Elkim Roa:
AES Sbox Acceleration Schemes for Low-Cost SoCs. ISCAS 2021: 1-5 - [c9]Ckristian Duran, Elkim Roa:
Routing-Aware Standard Cell Placement Algorithm Applying Boolean Satisfiability. ISCAS 2021: 1-5 - [c8]Ronaldo Serrano, Ckristian Duran, Trong-Thuc Hoang, Marco Sarmiento, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3. ISOCC 2021: 17-18 - [c7]Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Khai-Duy Nguyen, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham
A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications. ISOCC 2021: 375-376 - 2020
- [j3]Trong-Thuc Hoang
Quick Boot of Trusted Execution Environment With Hardware Accelerators. IEEE Access 8: 74015-74023 (2020) - [j2]Trong-Thuc Hoang
Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB). IEICE Electron. Express 17(20): 20200282 (2020) - [c6]Ckristian Duran, Megan Wachs, Luis E. Rueda G., Albert Huntington, Javier Ardila, Jack Kang, Andres Amaya, Héctor Gómez, Juan Romero, Laude Fernandez, Felipe Flechas, Rolando Torres, Juan Sebastian Moya, Wilmer Ramirez, Julian Arenas, Juan Gomez, Hanssel Morales
An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications. CICC 2020: 1-4 - [c5]Ckristian Duran, Hanssel Morales
Simulation and Formal: The Best of Both Domains for Instruction Set Verification of RISC-V Based Processors. ISCAS 2020: 1-4 - [c4]Trong-Thuc Hoang, Ckristian Duran, Akira Tsukamoto, Kuniyasu Suzaki
Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [j1]Héctor Gómez
Defeating Silicon Reverse Engineering Using a Layout-Level Standard Cell Camouflage. IEEE Trans. Consumer Electron. 65(1): 109-118 (2019) - [c3]Hanssel Morales
A Low-Area Direct Memory Access Controller Architecture for a RISC-V Based Low-Power Microcontroller. LASCAS 2019: 97-100 - 2018
- [c2]Héctor Gómez, Ckristian Duran, Elkim Roa
Standard cell camouflage method to counter silicon reverse engineering. ICCE 2018: 1-4 - 2016
- [c1]Ckristian Duran, D. Luis Rueda, Giovanny Castillo, Anderson Agudelo, Camilo Rojas, Luis Chaparro, Harry Hurtado, Juan Romero
A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC. LASCAS 2016: 315-318
Coauthor Index
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