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Jorge Juan-Chico
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2020 – today
- 2023
- [j6]German Cano-Quiveu
, Paulino Ruiz-De-Clavijo-Vazquez
IRIS: An embedded secure boot for IoT devices. Internet Things 23: 100874 (2023) - 2021
- [j5]German Cano-Quiveu
An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation. IEEE Access 9: 161383-161394 (2021) - 2020
- [j4]David Guerrero Martos
Using the complement of the cosine to compute trigonometric functions. EURASIP J. Adv. Signal Process. 2020(1): 1-21 (2020) - [j3]David Guerrero Martos, German Cano-Quiveu
Address-encoded byte order. Microprocess. Microsystems 78: 103268 (2020)
2000 – 2009
- 2007
- [j2]David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electron. 3(1): 70-77 (2007) - [c15]David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS 2007: 404-412 - 2006
- [j1]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero Martos, Enrique Ostúa
Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electron. 2(1): 87-94 (2006) - 2005
- [c14]Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. PATMOS 2005: 337-347 - [c13]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa
Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS 2005: 425-435 - 2004
- [c12]Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa
Signal Sampling Based Transition Modeling for Digital Gates Characterization. PATMOS 2004: 829-837 - 2003
- [c11]Alejandro Millán, Manuel J. Bellido
Internode: Internal Node Logic Computational Model. Annual Simulation Symposium 2003: 241-248 - [c10]David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán:
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS 2003: 501-510 - [e1]Jorge Juan-Chico, Enrico Macii:
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings. Lecture Notes in Computer Science 2799, Springer 2003, ISBN 3-540-20074-6 [contents] - 2002
- [c9]Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. PATMOS 2002: 353-362 - [c8]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. PATMOS 2002: 400-408 - [c7]Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). PATMOS 2002: 477-486 - 2001
- [c6]Paulino Ruiz-de-Clavijo
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE 2001: 467-471 - [c5]Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carmen Baena Oliva, Manuel Valencia
AUTODDM: automatic characterization tool for the delay degradation model. ICECS 2001: 1631-1634 - [c4]Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero:
Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) 2001: 483-486 - 2000
- [c3]Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia:
Inertial and degradation delay model for CMOS logic gates. ISCAS 2000: 459-462 - [c2]Jorge Juan-Chico, Manuel J. Bellido
Degradation Delay Model Extension to CMOS Gates. PATMOS 2000: 149-158 - [c1]Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. PATMOS 2000: 316-326
Coauthor Index
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