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Xingzhou Cheng
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2020 – today
- 2023
- [j2]Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao:
NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration. Sci. China Inf. Sci. 66(4) (2023) - 2022
- [j1]Jianlei Yang
, Wenzhi Fu, Xingzhou Cheng
S2 Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks. IEEE Trans. Computers 71(6): 1440-1452 (2022) - [i4]Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao:
NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration. CoRR abs/2204.09989 (2022) - 2021
- [i3]Jianlei Yang, Wenzhi Fu, Xingzhou Cheng, Xucheng Ye, Pengcheng Dai, Weisheng Zhao:
S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks. CoRR abs/2106.07894 (2021) - 2020
- [c3]Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo
SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training. DAC 2020: 1-6 - [c2]Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao:
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. DAC 2020: 1-6 - [i2]Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao:
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. CoRR abs/2007.10702 (2020) - [i1]Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen, Weisheng Zhao:
SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training. CoRR abs/2007.13595 (2020)
2010 – 2019
- 2016
- [c1]Xin Lu, Fei Su, Haozhang Liu, Weiwei Chen, Xingzhou Cheng:
A unified OLAP/OLTP big data processing framework in telecom industry. ISCIT 2016: 290-295
Coauthor Index
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