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Fangxu Lv
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2020 – today
- 2024
- [j12]Wenchen Wang, Fangxu Lv, Zhengbin Pang, Heng Huang, Zhang Luo, Xingyun Qi, Jiaqing Xu, Geng Zhang, Kewei Xin, Chengzhuo Zhao:
A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process. IEICE Electron. Express 21(19): 20240375 (2024) - [j11]Xiaoyue Hu, Fangxu Lv, Mingche Lai, Zhang Luo, Qiang Wang, Chaolong Xu, Ruotian Yin, Zhouhao Yang, Cewen Liu:
A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE. IEICE Electron. Express 21(19): 20240417 (2024) - [j10]Bolin Ren
, Fangxu Lv, Mingche Lai, Liquan Xiao, Geng Zhang, Xuqiang Zheng, Zhang Luo, Jiaqing Xu:
A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface. Microelectron. J. 152: 106326 (2024) - [j9]Meng Li
A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs. Microelectron. J. 152: 106330 (2024) - [j8]Zhang Luo, Sichun Du
Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization. IEEE Trans. Circuits Syst. I Regul. Pap. 71(4): 1745-1756 (2024) - [j7]Kewei Xin
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 11-15 (2024) - [c18]Yu He, Xuqiang Zhenq, Zedong Wang, Zunsong Yanq, Hua Xu, Fangxu Lv, Mingche Lai, Xinyu Liu:
An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM. CICC 2024: 1-2 - [c17]Chaolong Xu
FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver. ACM Great Lakes Symposium on VLSI 2024: 13-18 - 2023
- [j6]Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Zhaoyang Liu, Hua Xu, Weijie Li, Zhi Jin, Mingche Lai, Xinyu Liu:
A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology. Microelectron. J. 140: 105905 (2023) - [c16]Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu:
A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks. HPCC/DSS/SmartCity/DependSys 2023: 742-749 - [c15]Qing Liu, Heming Wang, Fangxu Lv, Geng Zhang, Dongbin Lv:
Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications. ICCEIC 2023: 216-220 - 2022
- [j5]Mingche Lai, Geng Zhang
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. Microelectron. J. 130: 105628 (2022) - 2021
- [c14]Geng Zhang
A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface. ASICON 2021: 1-4 - [c13]Tao Liu, Fangxu Lv, Bin Liang, Heming Wang, Jianye Wang, Miaomiao Wu:
An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits. ASICON 2021: 1-4 - [c12]Miaomiao Wu, Zhengbin Pang, Fangxu Lv, Jianjun Shi, Heming Wang, Tao Liu, Dechao Lu, Zheng Wang:
An Adaptive Equalization Algorithm for High Speed SerDes. ASICON 2021: 1-4 - 2020
- [j4]Xuqiang Zheng
Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators. IEEE J. Solid State Circuits 55(6): 1651-1664 (2020) - [j3]Xuqiang Zheng
A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS. IEEE J. Solid State Circuits 55(7): 1864-1876 (2020) - [c11]Zhengbin Pang, Fangxu Lv, Weiping Tang, Mingche Lai, Kaile Guo, Yuxuan Wu, Tao Liu, Miaomiao Wu, Dechao Lu:
A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology. ACA 2020: 31-42
2010 – 2019
- 2019
- [c10]Hao Ding, Xuqiang Zheng, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu:
A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS. ESSCIRC 2019: 195-198 - [c9]Dengjie Wang, Hong Chen, Wenhuan Luan, Xin Lin, Fangxu Lv, Ziqiang Wang, Hanjun Jiang, Chun Zhang, Zhihua Wang:
A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology. MWSCAS 2019: 251-254 - 2018
- [j2]Fangxu Lv, Xuqiang Zheng, Feng Zhao
A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications. Microelectron. J. 82: 36-45 (2018) - 2017
- [j1]Xuqiang Zheng
A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS. IEEE J. Solid State Circuits 52(11): 2963-2978 (2017) - [c8]Fangxu Lv, Jianye Wang, Dengjie Wang, Yongcong Liu, Ziqiang Wang:
Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology. ASICON 2017: 537-540 - [c7]Xuqiang Zheng, Fangxu Lv, Feng Zhao
A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS. CICC 2017: 1-4 - [c6]Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao
A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS. CICC 2017: 1-4 - [c5]Fangxu Lv, Xuqiang Zheng, Shuai Yuan, Ziqiang Wang, Yajun He, Chun Zhang, Zhihua Wang, Jianye Wang:
A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology. MWSCAS 2017: 539-542 - [c4]Yajun He, Ziqiang Wang, Han Liu, Fangxu Lv, Shuai Yuan, Chun Zhang, Zhihua Wang, Hanjun Jiang:
An 8.5-12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes. MWSCAS 2017: 791-794 - 2016
- [c3]Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao
A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. ESSCIRC 2016: 305-308 - 2015
- [c2]Fangxu Lv, Xuqiang Zheng, Ziqiang Wang, Jianye Wang, Fule Li:
A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology. ASICON 2015: 1-4 - 2014
- [c1]Yu Wang, Jincheng Zhang, Quan Wang, Fangxu Lv, Kewei Chen:
Compressive Spectrum Sensing Based on Sparse Sub-band Basis in Wireless Sensor Network. CWSN 2014: 52-58
Coauthor Index
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