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Juhyoung Lee
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2020 – today
- 2024
- [j13]Sangjin Kim
, Zhiyong Li
DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell. IEEE J. Solid State Circuits 59(1): 102-115 (2024) - 2023
- [j12]Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Juhyoung Lee, Hoi-Jun Yoo:
SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit. IEEE J. Solid State Circuits 58(10): 2812-2825 (2023) - [c25]Sangjin Kim, Zhiyong Li
DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching. ISSCC 2023: 256-257 - [c24]Wooyoung Jo, Sangjin Kim, Juhyoung Lee, Donghyeon Han, Sangyeob Kim, Seungyoon Choi, Hoi-Jun Yoo:
NeRPIM: A 4.2 mJ/frame Neural Rendering Processing-in-memory Processor with Space Encoding Block-wise Mapping for Mobile Devices. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j11]Juhyoung Lee
OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor With Dual-Mode Weight Compression and Sparse Weight Transposer. IEEE J. Solid State Circuits 57(4): 999-1012 (2022) - [j10]Juhyoung Lee
ECIM: Exponent Computing in Memory for an Energy-Efficient Heterogeneous Floating-Point DNN Training Processor. IEEE Micro 42(1): 99-107 (2022) - [j9]Donghyeon Han
A Mobile DNN Training Processor With Automatic Bit Precision Search and Fine-Grained Sparsity Exploitation. IEEE Micro 42(2): 16-25 (2022) - [j8]Sangyeob Kim
TSUNAMI: Triple Sparsity-Aware Ultra Energy-Efficient Neural Network Training Accelerator With Multi-Modal Iterative Pruning. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1494-1506 (2022) - [j7]Sangjin Kim
A Low-Power Graph Convolutional Network Processor With Sparse Grouping for 3D Point Cloud Semantic Segmentation in Mobile Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1507-1518 (2022) - [c23]Donghyeon Han, Dongseok Im, Gwangtae Park, Youngwoo Kim, Seokchan Song, Juhyoung Lee, Hoi-Jun Yoo:
A 0.95 mJ/frame DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation. AICAS 2022: 37-40 - [c22]Juhyoung Lee, Wooyoung Jo, Seong-Wook Park, Hoi-Jun Yoo:
Low-power Autonomous Adaptation System with Deep Reinforcement Learning. AICAS 2022: 300-303 - [c21]Donghyeon Han, Dongseok Im, Gwangtae Park, Youngwoo Kim, Seokchan Song, Juhyoung Lee, Hoi-Jun Yoo:
A DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation. AICAS 2022: 501 - [c20]Donghyeon Han, Dongseok Im, Gwangtae Park, Youngwoo Kim, Seokchan Song, Juhyoung Lee, Hoi-Jun Yoo:
HNPU-V2: A 46.6 FPS DNN Training Processor for Real-World Environmental Adaptation based Robust Object Detection on Mobile Devices. HCS 2022: 1-18 - 2021
- [j6]Ji-Hoon Kim
Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks. IEEE J. Solid State Circuits 56(4): 1093-1104 (2021) - [j5]Sanghoon Kang
GANPU: An Energy-Efficient Multi-DNN Training Processor for GANs With Speculative Dual-Sparsity Exploitation. IEEE J. Solid State Circuits 56(9): 2845-2857 (2021) - [j4]Donghyeon Han
HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching. IEEE J. Solid State Circuits 56(9): 2858-2869 (2021) - [c19]Juhyoung Lee, Changhyeon Kim, Donghyeon Han, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo:
Energy-Efficient Deep Reinforcement Learning Accelerator Designs for Mobile Autonomous Systems. AICAS 2021: 1-4 - [c18]Wooyoung Jo, Juhyoung Lee, Seunghyun Park, Hoi-Jun Yoo:
An Energy-Efficient Deep Reinforcement Learning FPGA Accelerator for Online Fast Adaptation with Selective Mixed-precision Re-training. A-SSCC 2021: 1-3 - [c17]Donghyeon Han, Dongseok Im, Gwangtae Park, Youngwoo Kim, Seokchan Song, Juhyoung Lee, Hoi-Jun Yoo:
An Energy-Efficient Deep Neural Network Training Processor with Bit-Slice-Level Reconfigurability and Sparsity Exploitation. COOL CHIPS 2021: 1-3 - [c16]Sangjin Kim, Juhyoung Lee, Dongseok Im, Hoi-Jun Yoo:
PNNPU: A Fast and Efficient 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access. HCS 2021: 1-23 - [c15]Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Donghyeon Han, Jinsu Lee, Hoi-Jun Yoo:
An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory. HCS 2021: 1-20 - [c14]Juhyoung Lee, Sangyeob Kim, Ji-Hoon Kim, Sangjin Kim, Wooyoung Jo, Donghyeon Han, Hoi-Jun Yoo:
OmniDRL: An Energy-Efficient Mobile Deep Reinforcement Learning Accelerators with Dual-mode Weight Compression and Direct Processing of Compressed Data. HCS 2021: 1-21 - [c13]Sangjin Kim, Juhyoung Lee, Dongseok Im, Hoi-Jun Yoo:
PNNPU: A 11.9 TOPS/W High-speed 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access. VLSI Circuits 2021: 1-2 - [c12]Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Jinsu Lee, Hoi-Jun Yoo:
A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory. VLSI Circuits 2021: 1-2 - [c11]Juhyoung Lee, Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Donghyeon Han, Jinsu Lee, Hoi-Jun Yoo:
OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer. VLSI Circuits 2021: 1-2 - [i1]Juhyoung Lee, Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Hoi-Jun Yoo:
GST: Group-Sparse Training for Accelerating Deep Reinforcement Learning. CoRR abs/2101.09650 (2021) - 2020
- [j3]Juhyoung Lee
SRNPU: An Energy-Efficient CNN-Based Super-Resolution Processor With Tile-Based Selective Super-Resolution in Mobile Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 320-334 (2020) - [j2]Sangyeob Kim
A Power-Efficient CNN Accelerator With Similar Feature Skipping for Face Recognition in Mobile Devices. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4): 1181-1193 (2020) - [c10]Sangjin Kim, Sangyeob Kim, Juhyoung Lee, Hoi-Jun Yoo:
A 54.7 fps 3D Point Cloud Semantic Segmentation Processor with Sparse Grouping Based Dilated Graph Convolutional Network for Mobile Devices. ISCAS 2020: 1-5 - [c9]Sanghoon Kang, Donghyeon Han, Juhyoung Lee, Dongseok Im, Sangyeob Kim, Soyeon Kim, Hoi-Jun Yoo:
7.4 GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation. ISSCC 2020: 140-142 - [c8]Sangyeob Kim, Juhyoung Lee, Sanghoon Kang, Jinmook Lee, Hoi-Jun Yoo:
A 146.52 TOPS/W Deep-Neural-Network Learning Processor with Stochastic Coarse-Fine Pruning and Adaptive Input/Output/Weight Skipping. VLSI Circuits 2020: 1-2 - [c7]Ji-Hoon Kim, Juhyoung Lee, Jinsu Lee, Hoi-Jun Yoo, Joo-Young Kim:
Z-PIM: An Energy-Efficient Sparsity Aware Processing-In-Memory Architecture with Fully-Variable Weight Precision. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c6]Sangyeob Kim, Juhyoung Lee, Sanghoon Kang, Jinsu Lee, Hoi-Jun Yoo:
A 15.2 TOPS/W CNN Accelerator with Similar Feature Skipping for Face Recognition in Mobile Devices. ISCAS 2019: 1-5 - [c5]Jinsu Lee, Juhyoung Lee, Donghyeon Han, Jinmook Lee, Gwangtae Park, Hoi-Jun Yoo:
LNPU: A 25.3TFLOPS/W Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of FP8-FP16. ISSCC 2019: 142-144 - [c4]Juhyoung Lee, Dongjoo Shin, Jinsu Lee, Jinmook Lee, Sanghoon Kang, Hoi-Jun Yoo:
A Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices. VLSI Circuits 2019: 302- - 2018
- [j1]Dongjoo Shin, Jinmook Lee, Jinsu Lee, Juhyoung Lee, Hoi-Jun Yoo:
DNPU: An Energy-Efficient Deep-Learning Processor with Heterogeneous Multi-Core Architecture. IEEE Micro 38(5): 85-93 (2018) - [c3]Juhyoung Lee, Changhyeon Kim, Sungpill Choi, Dongjoo Shin, Sanghoon Kang, Hoi-Jun Yoo:
A 46.1 fps Global Matching Optical Flow Estimation Processor for Action Recognition in Mobile Devices. ISCAS 2018: 1-5 - 2017
- [c2]Dongjoo Shin, Jinmook Lee, Jinsu Lee, Juhyoung Lee, Hoi-Jun Yoo:
An energy-efficient deep learning processor with heterogeneous multi-core architecture for convolutional neural networks and recurrent neural networks. COOL Chips 2017: 1-2
2000 – 2009
- 2004
- [c1]Juhyoung Lee, Youngil Youm, Wan Kyun Chung:
The Development of Postech Hand 5. ICRA 2004: 3386-3390
Coauthor Index
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