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Ankesh Jain
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2020 – today
- 2024
- [j7]Pratibha Verma
, Sourav Naval
Hybrid Piezoelectric-Triboelectric Biomechanical Harvesting System for Wearable Applications. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1914-1918 (2024) - [c18]Shivani, Ankesh Jain:
Analysis and Design of High-Speed, Linear and Fullscale Input Swing Voltage to Time Converters. PRIME 2024: 1-4 - 2023
- [c17]Sayan Banerjee, Ankesh Jain:
Modified Gm-Free Assisted Opamp Technique in Continuous Time Delta Sigma Modulators. APCCAS 2023: 154-158 - [c16]Aditya Shahane, Saripilli Swapna Manjiri, Ankesh Jain, Sandeep Kumar:
Graph of Circuits with GNN for Exploring the Optimal Design Space. NeurIPS 2023 - 2021
- [c15]Ankesh Jain
High speed Continuous-time Delta Sigma Modulators for Wide-band Applications: A review paper. ISOCC 2021: 250-251 - [c14]Jatin Sharma, Pratibha Verma
Electrical Energy Injection using Hybrid SECE for High Performance Nonlinear Mechanical Energy Harvesting. MWSCAS 2021: 80-83 - 2020
- [j6]Liang Qi
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance. IEEE J. Solid State Circuits 55(2): 344-355 (2020) - [c13]Janak Sharda
Reduction of the Weight-Decay Rate of Volatile Memory Synapses in an Analog Hardware Neural Network for Accurate and Scalable On-Chip Learning. ICONS 2020: 13:1-13:8 - [c12]Mounika Kundurthi, Dhiman Mallick, Ankesh Jain:
System Level Modeling and Optimization of Hybrid Vibration Energy Harvesters. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j5]Yanquan Luo
Input Referred Comparator Noise in SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 718-722 (2019) - [c11]Mahdi Rajabzadeh, Matthias Häberle, Ankesh Jain
An Integrated Readout for Current Sensing based on a Σ∆ Modulator with Switched Capacitor Feedback. ESSCIRC 2019: 321-324 - [c10]Ankesh Jain
Effective Filtering of Requantization Error in Dual Quantized CTDSM using FIR DAC. ISCAS 2019: 1-5 - [c9]Liang Qi, Ankesh Jain
A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS. ISSCC 2019: 336-338 - 2018
- [j4]Lishan Lv
A 0.4-V Gm-C Proportional-Integrator-Based Continuous-Time ΔΣ Modulator With 50-kHz BW and 74.4-dB SNDR. IEEE J. Solid State Circuits 53(11): 3256-3267 (2018) - [j3]Ankesh Jain
Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 434-443 (2018) - [c8]Jiazuo Chi, Ankesh Jain
Interferer Induced Jitter Reduction in Bandpass CT ΣΔ Modulators for Receiver Applications. ISCAS 2018: 1-4 - [c7]Ankesh Jain
Gain Mismatch Insensitive Time-Interleaved DAC for CT Delta Sigma Modulator by application of a Three-State DAC. ISCAS 2018: 1-5 - [c6]Yanquan Luo, Liang Qi, Ankesh Jain
A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch. ISCAS 2018: 1-5 - 2017
- [c5]Tripti Jain, Klaus Schneider
An Efficient Self-Routing and Non-Blocking Interconnection Network on Chip. NoCArc@MICRO 2017: 4:1-4:6 - [c4]Tripti Jain, Klaus Schneider
Deriving concentrators from binary sorters using half cleaners. ReConFig 2017: 1-6 - 2016
- [c3]Ankesh Jain
A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback. VLSI Circuits 2016: 1-2 - 2014
- [j2]Ankesh Jain
Characterization Techniques for High Speed Oversampled Data Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1313-1320 (2014) - 2013
- [c2]Ankesh Jain
Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface. ISCAS 2013: 1252-1255 - 2012
- [j1]Ankesh Jain
Analysis and Design of a High Speed Continuous-time ΔΣ Modulator Using the Assisted Opamp Technique. IEEE J. Solid State Circuits 47(7): 1615-1625 (2012) - 2011
- [c1]Ankesh Jain
A 4mW 1 GS/s continuous-time ΔΣ modulator with 15.6MHz bandwidth and 67 dB dynamic range. ESSCIRC 2011: 259-262
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