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SungWon Chung
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2020 – today
- 2021
- [c6]SungWon Chung, Makoto Nakai, Samer B. Idres, Yongwei Ni, Hossein Hashemi:
19.1 Optical Phased-Array FMCW LiDAR with On-Chip Calibration. ISSCC 2021: 286-288 - [c5]Do-Yeon Yoon, Sonal Pinto, SungWon Chung, Paul Merolla, Thong-Wei Koh, Dongjin Seo:
A 1024-Channel Simultaneous Recording Neural SoC with Stimulation and Real-Time Spike Detection. VLSI Circuits 2021: 1-2
2010 – 2019
- 2019
- [j10]SungWon Chung, Jiemi Wang:
Tightly Coupled Machine Learning Coprocessor Architecture With Analog In-Memory Computing for Instruction-Level Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(3): 544-561 (2019) - 2018
- [j9]SungWon Chung, Hooman Abediasl, Hossein Hashemi:
A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS. IEEE J. Solid State Circuits 53(1): 275-296 (2018) - [j8]Zhanghao Yu, Xi Yang, SungWon Chung:
A Compact Operational Amplifier with Load-Insensitive Stability Compensation for High-Precision Transducer Interface. Sensors 18(2): 393 (2018) - [c4]SungWon Chung, Makoto Nakai, Edward Preisler, Hossein Hashemi:
Poly-Crystalline Silicon Waveguide Devices on Hollow Deep Trench Isolation in Standard Foundry Bulk Silicon Process. OFC 2018: 1-3 - 2017
- [c3]SungWon Chung, Hooman Abediasl, Hossein Hashemi:
15.4 A 1024-element scalable optical phased array in 0.18µm SOI CMOS. ISSCC 2017: 262-263 - 2016
- [i1]SungWon Chung:
The Design of the NetBSD I/O Subsystems. CoRR abs/1605.05810 (2016) - 2015
- [c2]SungWon Chung, Hae-Seung Lee:
A 200-MS/s 98-dB SNR track-and-hold in 0.25-um GaN HEMT. CICC 2015: 1-4 - [c1]SungWon Chung, Rui Ma, Koon Hoo Teo, Kieran Parsons:
Outphasing multi-level RF-PWM signals for inter-band carrier aggregation in digital transmitters. RWS 2015: 212-214 - 2014
- [b1]SungWon Chung:
Energy-efficient wireless transmitter architecture for mobile multimedia. Massachusetts Institute of Technology, Cambridge, MA, USA, 2014 - 2012
- [j7]Philip A. Godoy, SungWon Chung, Taylor W. Barton, David J. Perreault, Joel L. Dawson:
A 2.4-GHz, 27-dBm Asymmetric Multilevel Outphasing Power Amplifier in 65-nm CMOS. IEEE J. Solid State Circuits 47(10): 2372-2384 (2012) - 2011
- [j6]Hyun Ho Boo, SungWon Chung, Joel L. Dawson:
Digitally Assisted Feedforward Compensation of Cartesian-Feedback Power-Amplifier Systems. IEEE Trans. Circuits Syst. II Express Briefs 58-II(8): 457-461 (2011) - 2010
- [j5]SungWon Chung, Blandine Courcot, Michaël Sdika, Kristin Moffat, Caroline D. Rae, Roland G. Henry:
Bootstrap quantification of cardiac pulsation artifact in DTI. NeuroImage 49(1): 631-640 (2010)
2000 – 2009
- 2009
- [j4]Hyun Ho Boo, SungWon Chung, Joel L. Dawson:
Adaptive Predistortion Using a DeltaSigma Modulator for Automatic Inversion of Power Amplifier Nonlinearity. IEEE Trans. Circuits Syst. II Express Briefs 56-II(12): 901-905 (2009) - 2008
- [j3]Jeffrey I. Berman, SungWon Chung, Pratik Mukherjee, Christopher Paul Hess, Eric T. Han, Roland G. Henry:
Probabilistic streamline q-ball tractography using the residual bootstrap. NeuroImage 39(1): 215-222 (2008) - [j2]SungWon Chung, Daniel Pelletier, Michaël Sdika, Ying Lu, Jeffrey I. Berman, Roland G. Henry:
Whole brain voxel-wise analysis of single-subject serial DTI by permutation testing. NeuroImage 39(4): 1693-1705 (2008) - 2006
- [j1]SungWon Chung, Ying Lu, Roland G. Henry:
Comparison of bootstrap approaches for estimation of uncertainties of DTI parameters. NeuroImage 33(2): 531-541 (2006)
Coauthor Index
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