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Dominik Sisejkovic
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2020 – today
- 2024
- [i18]Lennart M. Reimann, Anschul Prashar, Chiara Ghinami, Rebecca Pelke, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL. CoRR abs/2401.17819 (2024) - 2023
- [j5]Niclas Ilg
, Paul Duplys, Dominik Sisejkovic, Michael Menth:
A survey of contemporary open-source honeypots, frameworks, and tools. J. Netw. Comput. Appl. 220: 103737 (2023) - [c28]Felix Staudigl
Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. CODES+ISSS 2023: 44-45 - [c27]Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. DAC 2023: 1-6 - [c26]Zeng Wang, Lilas Alrahis, Dominik Sisejkovic, Ozgur Sinanoglu:
AutoLock: Automatic Design of Logic Locking with Evolutionary Computation. DSN-S 2023: 200-202 - [c25]Anand Raj, Nikhitha Avula, Pabitra Das
DeepAttack: A Deep Learning Based Oracle-less Attack on Logic Locking. ISCAS 2023: 1-5 - [c24]Lennart M. Reimann
Quantitative Information Flow for Hardware: Advancing the Attack Landscape. LASCAS 2023: 1-4 - [c23]Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Veiras Bolzani Poehls, Rainer Leupers:
Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware. LATS 2023: 1-6 - [c22]Elmira Moussavi, Animesh Singh, Dominik Sisejkovic, Aravind Padma Kumar, Daniyar Kizatov, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri
Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. NEWCAS 2023: 1-5 - [c21]Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. VLSI-SoC 2023: 1-6 - [i17]Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Leticia Bolzani Poehls, Rainer Leupers:
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. CoRR abs/2302.07655 (2023) - [i16]Elmira Moussavi, Animesh Singh, Dominik Sisejkovic, Aravind Padma Kumar, Daniyar Kizatov, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri
Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. CoRR abs/2304.05686 (2023) - [i15]Zeng Wang, Lilas Alrahis, Dominik Sisejkovic, Ozgur Sinanoglu:
AutoLock: Automatic Design of Logic Locking with Evolutionary Computation. CoRR abs/2305.01840 (2023) - [i14]Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers:
Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. CoRR abs/2308.02400 (2023) - [i13]Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. CoRR abs/2308.02694 (2023) - 2022
- [b1]Dominik Sisejkovic:
Designing trustworthy hardware with logic locking. RWTH Aachen University, Germany, 2022 - [j4]Dominik Sisejkovic
Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1716-1729 (2022) - [c20]Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. AICAS 2022: 174-177 - [c19]Dominik Sisejkovic, Luca Collini
Designing ML-resilient locking at register-transfer level. DAC 2022: 769-774 - [c18]Felix Staudigl, Hazem Al Indari, Daniel Schön
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. DATE 2022: 1181-1184 - [c17]Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu
pHGen: A pH-Based Key Generation Mechanism Using ISFETs. HOST 2022: 61-64 - [c16]Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. LATS 2022: 1-4 - [i12]Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant:
pHGen: A pH-Based Key Generation Mechanism Using ISFETs. CoRR abs/2202.12085 (2022) - [i11]Dominik Sisejkovic
Designing ML-Resilient Locking at Register-Transfer Level. CoRR abs/2203.05399 (2022) - [i10]Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. CoRR abs/2204.01501 (2022) - [i9]Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. CoRR abs/2208.04769 (2022) - [i8]Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers:
Quantitative Information Flow for Hardware: Advancing the Attack Landscape. CoRR abs/2211.16891 (2022) - 2021
- [j3]Dominik Sisejkovic
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. ACM J. Emerg. Technol. Comput. Syst. 17(3): 30:1-30:26 (2021) - [c15]Shubham Rai
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? DATE 2021: 1905-1914 - [c14]Lennart M. Reimann
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. ICCD 2021: 603-607 - [c13]Dominik Sisejkovic
Trustworthy Hardware Design with Logic Locking. VLSI-SoC 2021: 1-2 - [c12]Dominik Sisejkovic
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. VLSI-SoC 2021: 1-6 - [c11]Farhad Merchant, Dominik Sisejkovic
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. VLSID 2021: 270-275 - [i7]Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers:
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. CoRR abs/2101.05591 (2021) - [i6]Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers:
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. CoRR abs/2107.01915 (2021) - [i5]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers:
Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks. CoRR abs/2107.08695 (2021) - [i4]Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. CoRR abs/2109.02379 (2021) - [i3]Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers:
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. CoRR abs/2112.01087 (2021) - 2020
- [c10]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann
Scaling Logic Locking Schemes to Multi-module Hardware Designs. ARCS 2020: 138-152 - [c9]Dominik Sisejkovic
A secure hardware-software solution based on RISC-V, logic locking and microkernel. SCOPES 2020: 62-65 - [i2]Dominik Sisejkovic
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. CoRR abs/2011.10389 (2020)
2010 – 2019
- 2019
- [c8]Dominik Sisejkovic
Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. ETS 2019: 1-6 - [c7]Dominik Sisejkovic
Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans. ACM Great Lakes Symposium on VLSI 2019: 27-32 - [c6]Dominik Sisejkovic
Protecting the Integrity of Processor Cores with Logic Encryption. SoCC 2019: 424-425 - [c5]Dominik Sisejkovic
A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms. VLSI-DAT 2019: 1-4 - 2018
- [j2]Mateja Dumic, Dominik Sisejkovic
Evolving priority rules for resource constrained project scheduling problem with genetic programming. Future Gener. Comput. Syst. 86: 211-221 (2018) - [c4]Dominik Sisejkovic
A Unifying logic encryption security metric. SAMOS 2018: 179-186 - 2017
- [j1]Stjepan Picek, Dominik Sisejkovic
Immunological algorithms paradigm for construction of Boolean functions with good cryptographic properties. Eng. Appl. Artif. Intell. 62: 320-330 (2017) - 2016
- [c3]Stjepan Picek, Dominik Sisejkovic, Domagoj Jakobovic
Extreme Pipelining Towards the Best Area-Performance Trade-Off in Hardware. AFRICACRYPT 2016: 147-166 - [c2]Stjepan Picek, Dominik Sisejkovic, Vladimir Rozic, Bohan Yang, Domagoj Jakobovic
Evolving Cryptographic Pseudorandom Number Generators. PPSN 2016: 613-622 - 2014
- [c1]Lejla Batina, Domagoj Jakobovic
S-box Pipelining Using Genetic Algorithms for High-Throughput AES Implementations: How Fast Can We Go? INDOCRYPT 2014: 322-337 - [i1]Lejla Batina, Domagoj Jakobovic, Nele Mentens, Stjepan Picek, Antonio de la Piedra, Dominik Sisejkovic:
S-box pipelining using genetic algorithms for high-throughput AES implementations: How fast can we go? IACR Cryptol. ePrint Arch. 2014: 734 (2014)
Coauthor Index
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Leticia Bolzani Poehls
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last updated on 2024-10-07 21:20 CEST by the dblp team
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