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Jeremy Yung Shern Low
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2010 – 2019
- 2016
- [j7]Thian Fatt Tay, Chip-Hong Chang
, Jeremy Yung Shern Low:
Erratum to "Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS {2n-1, 2n, 2n+1}". IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1612 (2016) - 2013
- [j6]Jeremy Yung Shern Low, Chip-Hong Chang
A New Approach to the Design of Efficient Residue Generators for Arbitrary Moduli. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9): 2366-2374 (2013) - [j5]Thian Fatt Tay, Chip-Hong Chang
Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n}, 2^{n}+1\}}$. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1936-1940 (2013) - [c8]Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
A signed integer programmable power-of-two scaler for {2n-1, 2n, 2n+1} RNS. ISCAS 2013: 2211-2214 - 2012
- [j4]Jeremy Yung Shern Low, Chip-Hong Chang
A VLSI Efficient Programmable Power-of-Two Scaler for 2n-1, 2n, 2n+1 RNS. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(12): 2911-2919 (2012) - [c7]Howard Tang, Joshua Yung Lih Low, Jeremy Yung Shern Low, Liter Siek
A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. APCCAS 2012: 272-275 - [c6]Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
A unified {2n-1, 2n, 2n+1} RNS scaler with dual scaling constants. APCCAS 2012: 296-299 - [c5]Joshua Yung Lih Low, Ching-Chuen Jong
A fast and compact circuit for integer square root computation based on Mitchell logarithmic method. ISCAS 2012: 1235-1238 - 2011
- [j3]Anh-Tuan Do, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong, Xiaoliang Tan, Kiat Seng Yeo
An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1252-1263 (2011) - [j2]Chip-Hong Chang
Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set 2n - 1, 2n, 2n + 1. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(11): 2686-2697 (2011) - [j1]Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo
Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 196-204 (2011) - [c4]Jeremy Yung Shern Low, Chip-Hong Chang
A new RNS scaler for {2n - 1, 2n, 2n + 1}. ISCAS 2011: 1431-1434 - 2010
- [c3]Anh-Tuan Do, Kiat Seng Yeo
An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving. APCCAS 2010: 704-707 - [c2]Manas Ranjan Meher, Ching-Chuen Jong
A novel counter-based low complexity inner-product architecture for high speed inputs. ISCAS 2010: 705-708
2000 – 2009
- 2008
- [c1]Anh-Tuan Do, Jeremy Yung Shern Low, Zhi-Hui Kong, Kiat Seng Yeo
A full current-mode sense amplifier for low-power SRAM applications. APCCAS 2008: 1402-1405
Coauthor Index
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