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Renan Netto
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2020 – today
- 2024
- [j4]Tiago Augusto Fontana
, Erfan Aghaeekiasaraee
ILPGRC: ILP-Based Global Routing Optimization With Cell Movements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 352-365 (2024) - 2023
- [j3]Erfan Aghaeekiasaraee
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes. ACM Trans. Design Autom. Electr. Syst. 28(5): 79:1-79:42 (2023) - 2022
- [j2]Renan Netto
Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1481-1494 (2022) - [c13]Erfan Aghaeekiasaraee, Aysa Fakheri Tabrizi, Tiago Augusto Fontana, Renan Netto, Sheiny Fabre Almeida, Upma Gandhi, José Luís Gützel, David T. Westwick, Laleh Behjat:
CR&P: An Efficient Co-operation between Routing and Placement. DATE 2022: 772-777 - [c12]Sheiny Fabre Almeida, Aysa Fakheri Tabrizi, Erfan Aghaeekiasaraee, Renan Netto, Tiago Augusto Fontana, Upma Gandhi, José Luís Güntzel, Laleh Behjat
E-RVP: An Initial Design Rule Violation Predictor Using Placement Information. ICECS 2022 2022: 1-4 - 2021
- [c11]Tiago Augusto Fontana, Erfan Aghaeekiasaraee, Renan Netto, Sheiny Fabre Almeida, Upma Gandhi, Aysa Fakheri Tabrizi, David T. Westwick, Laleh Behjat
ILP-Based Global Routing Optimization with Cell Movements. ISVLSI 2021: 25-30
2010 – 2019
- 2019
- [c10]Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius S. Livramento, Laércio Lima Pilla
How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization. ISPD 2019: 3-10 - 2018
- [c9]Sheiny Fabre, José Luís Güntzel, Laércio Lima Pilla
Enhancing Multi-Threaded Legalization Through k-d Tree Circuit Partitioning. SBCCI 2018: 1-6 - 2017
- [c8]Tiago Fontana, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Sheiny Almeida, Laércio Lima Pilla
How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library. ISPD 2017: 25-31 - [c7]Tiago Augusto Fontana, Sheiny Almeida, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Laércio Lima Pilla
Exploiting cache locality to speedup register clustering. SBCCI 2017: 191-197 - 2016
- [j1]Vinicius S. Livramento, Renan Netto, Chrystian Guth, José Luís Güntzel, Luiz Cláudio Villar dos Santos
Clock-Tree-Aware Incremental Timing-Driven Placement. ACM Trans. Design Autom. Electr. Syst. 21(3): 38:1-38:27 (2016) - [c6]Renan Netto, Chrystian Guth, Vinicius S. Livramento, Márcio Castro
Exploiting parallelism to speed up circuit legalization. ICECS 2016: 624-627 - [c5]Renan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos
Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees. ISVLSI 2016: 36-41 - [c4]Renan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos
Evaluating the impact of circuit legalization on incremental optimization techniques. SBCCI 2016: 1-6 - 2015
- [c3]Vinicius S. Livramento, Chrystian Guth, Renan Netto, José Luís Almada Güntzel, Luiz C. V. dos Santos
Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization. ICCAD 2015: 528-535 - [c2]Chrystian Guth, Vinicius S. Livramento, Renan Netto, Renan Fonseca, José Luís Güntzel, Luiz C. V. dos Santos
Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression. ISPD 2015: 141-148 - 2013
- [c1]Edson Sorato, Renan Netto, Pedro Michel, José Luís Güntzel, Adalbery R. Castro, Aldebaro Klautau
VLSI architectures for Digital Modulation Classification using Support Vector Machines. LASCAS 2013: 1-4
Coauthor Index
aka: José Luís Almada Güntzel
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