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Dongbing Fu
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2020 – today
- 2024
- [j5]Xiaodan Zhou, Weipeng He, Dongbing Fu, Jianan Wang, Guangbing Chen:
A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS. IEICE Electron. Express 21(7): 20240038 (2024) - [j4]Xiaodan Zhou
, Weipeng He, Dongbing Fu, Jianan Wang, Guangbing Chen, Qiang Li:
A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS. Microelectron. J. 146: 106144 (2024) - [c3]Xiaodan Zhou, Weipeng He, Chen Su, Tao Liu, Dongbing Fu, Qiang Li:
A Low Power 16-bit 125MS/s Pipeline ADC with 100dB SFDR. ISCAS 2024: 1-5 - 2021
- [j3]Peng Yin
A Low-Area and Low-Power Comma Detection and Word Alignment Circuits for JESD204B/C Controller. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2925-2935 (2021) - 2020
- [j2]Zhou Shu
A 5-13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process. IEEE Trans. Circuits Syst. 67-I(10): 3378-3388 (2020)
2010 – 2019
- 2019
- [c2]Jun Liu, Xianjie Wan, Mingyuan Xu, Youhua Wang, Yi Ding, Dongbing Fu:
A High Speed Clock Receiver for DAC with Cross point and Duty Cycle Adjustable Capability. ICITEE 2019: 62:1-62:4 - 2018
- [j1]Gang Chen, Min Gong, Dongbing Fu, Junan Zhang:
A high efficient CTLE for 12.5 Gbps receiver of JESD204B standard. IEICE Electron. Express 15(15): 20180617 (2018) - 2013
- [c1]Ting Li, Dongbing Fu, Yong Zhang, Yan Wang, Lu Liu, Xu Wang:
A high-speed front-end circuit used in a 16bit 250MSPS pipelined ADC. ASICON 2013: 1-4
Coauthor Index
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