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Davide Giri
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2020 – today
- 2024
- [c21]Vignesh Suresh
, Bakshree Mishra
Mozart: Taming Taxes and Composing Accelerators with Shared-Memory. PACT 2024: 183-200 - [c20]Martin Cochet, Karthik Swaminathan, Erik Jens Loscalzo, Joseph Zuckerman, Maico Cassel dos Santos, Davide Giri, Alper Buyuktosunoglu, Tianyu Jia, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Luca P. Carloni, Pradip Bose:
BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs. ISCA 2024: 801-817 - [c19]Maico Cassel dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita V. Adve, Pradip Bose, David Brooks, Luca P. Carloni, Kenneth L. Shepard, Gu-Yeon Wei:
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. ISSCC 2024: 262-264 - [c18]Erik Jens Loscalzo, Martin Cochet, Joseph Zuckerman, Samira Zalias, Michael Lekas, Stephen Cahill, Tianyu Jia, Karthik Swaminathan, Maico Cassel dos Santos, Davide Giri, Hesam Sadeghi, Joseph Meyer, Noah Sturcken, David Brooks, Gu-Yeon Wei, Luca P. Carloni, Pradip Bose, Kenneth L. Shepard:
A 400-ns-Settling- Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j5]Gabriele Tombesi
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs. IEEE Des. Test 40(6): 64-75 (2023) - [c17]Fei Gao, Ting-Jung Chang, Ang Li
DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET. CICC 2023: 1-2 - [c16]Biruk B. Seyoum, Davide Giri, Kuan-Lin Chiu, Bryce Natter, Luca P. Carloni:
PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs. DATE 2023: 1-6 - [c15]Kuan-Lin Chiu, Davide Giri, Luca Piccolboni, Luca P. Carloni:
An Analysis of Accelerator Data-Transfer Modes in NoC-Based SoC Architectures. HPEC 2023: 1-7 - [c14]Thierry Tambe
A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management. ISSCC 2023: 342-343 - 2022
- [j4]Luca Piccolboni
Accelerators & Security: The Socket Approach. IEEE Comput. Archit. Lett. 21(2): 65-68 (2022) - [c13]Biruk B. Seyoum, Davide Giri, Kuan-Lin Chiu, Luca P. Carloni:
Work-in-Progress: An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs. CASES 2022: 25-26 - [c12]Tianyu Jia, Paolo Mantovani, Maico Cassel dos Santos, Davide Giri, Joseph Zuckerman, Erik Jens Loscalzo, Martin Cochet, Karthik Swaminathan, Gabriele Tombesi, Jeff Jun Zhang, Nandhini Chandramoorthy, John-David Wellman, Kevin Tien, Luca P. Carloni, Kenneth L. Shepard, David Brooks, Gu-Yeon Wei, Pradip Bose:
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC. ESSCIRC 2022: 269-272 - [c11]Maico Cassel dos Santos, Tianyu Jia, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Luca P. Carloni, Pradip Bose:
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components. ICCAD 2022: 20:1-20:9 - [i6]Joseph Zuckerman, Paolo Mantovani, Davide Giri, Luca P. Carloni:
Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP. CoRR abs/2206.01901 (2022) - 2021
- [j3]Davide Giri
Accelerator Integration for Open-Source SoC Design. IEEE Micro 41(4): 8-14 (2021) - [c10]Guy Eichler, Luca Piccolboni, Davide Giri, Luca P. Carloni
MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces. ICCD 2021: 101-108 - [c9]Joseph Zuckerman, Davide Giri, Jihye Kwon
Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs. MICRO 2021: 350-365 - [i5]Joseph Zuckerman, Davide Giri, Jihye Kwon, Paolo Mantovani, Luca P. Carloni:
Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs. CoRR abs/2109.06382 (2021) - [i4]Allison McCarn Deiana, Nhan Tran, Joshua Agar, Michaela Blott, Giuseppe Di Guglielmo, Javier M. Duarte
Applications and Techniques for Fast Machine Learning in Science. CoRR abs/2110.13041 (2021) - 2020
- [c8]Paolo Mantovani, Robert Margelli, Davide Giri, Luca P. Carloni
HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis. CICC 2020: 1-8 - [c7]Davide Giri, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca P. Carloni:
ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning. DATE 2020: 1049-1054 - [c6]Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni
Agile SoC Development with Open ESP : Invited Paper. ICCAD 2020: 96:1-96:9 - [c5]Opeoluwa Matthews, Aninda Manocha, Davide Giri, Marcelo Orenes-Vera, Esin Tureci, Tyler Sorensen
MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems. ISPASS 2020: 136-148 - [i3]Davide Giri, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca P. Carloni:
ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning. CoRR abs/2004.03640 (2020) - [i2]Opeoluwa Matthews, Aninda Manocha, Davide Giri, Marcelo Orenes-Vera, Esin Tureci, Tyler Sorensen, Tae Jun Ham, Juan L. Aragón, Luca P. Carloni, Margaret Martonosi:
The MosaicSim Simulator (Full Technical Report). CoRR abs/2004.07415 (2020) - [i1]Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni:
Agile SoC Development with Open ESP. CoRR abs/2009.01178 (2020)
2010 – 2019
- 2019
- [c4]Davide Giri, Paolo Mantovani, Luca P. Carloni:
Runtime reconfigurable memory hierarchy in embedded scalable platforms. ASP-DAC 2019: 719-726 - [c3]Luca P. Carloni, Emilio G. Cota, Giuseppe Di Guglielmo, Davide Giri, Jihye Kwon
Teaching Heterogeneous Computing with System-Level Design Methods. WCAE@ISCA 2019: 4:1-4:8 - 2018
- [j2]Davide Giri
Accelerators and Coherence: An SoC Perspective. IEEE Micro 38(6): 36-45 (2018) - [j1]Davide Giri, Giovanni Causapruno, Fabrizio Riente
Parallel and Serial Computation in Nanomagnet Logic: An Overview. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1427-1437 (2018) - [c2]Davide Giri, Paolo Mantovani, Luca P. Carloni:
NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators. NOCS 2018: 1:1-1:8 - 2014
- [c1]Davide Giri, Marco Vacca, Giovanni Causapruno, Wenjing Rao, Mariagrazia Graziano, Maurizio Zamboni
A standard cell approach for MagnetoElastic NML circuits. NANOARCH 2014: 65-70
Coauthor Index
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last updated on 2024-11-04 20:42 CET by the dblp team
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