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Katsuyuki Sakuma
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2020 – today
- 2020
- [j5]Gaddi Blumrosen
, Katsuyuki Sakuma
Back to Finger-Writing: Fingertip Writing Technology Based on Pressure Sensing. IEEE Access 8: 35455-35468 (2020)
2010 – 2019
- 2019
- [c8]Katsuyuki Sakuma, Gaddi Blumrosen
Turning the Finger into a Writing Tool. EMBC 2019: 1239-1242 - 2013
- [c7]Keiji Matsumoto, Soichiro Ibaraki, Kuniaki Sueoka, Katsuyuki Sakuma
Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack. 3DIC 2013: 1-8 - 2011
- [c6]Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Takeda, Katsuyuki Sakuma
Chip-level TSV integration for rapid prototyping of 3D system LSIs. 3DIC 2011: 1-4 - [c5]Sayuri Kohara, Akihiro Horibe, Kuniaki Sueoka, Keiji Matsumoto, Fumiaki Yamada, Yasumitsu Orii, Katsuyuki Sakuma
Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration. 3DIC 2011: 1-7 - [c4]Akiko Okada, Masatsugu Nimura, Naoko Unami, Akitsu Shigetou, Hirokazu Noma
Low temperature Au-Au bonding with VUV/O3 treatment. 3DIC 2011: 1-5 - 2010
- [c3]Akihiro Horibe, Kuniaki Sueoka, Katsuyuki Sakuma
High density 3D integration by pre-applied Inter Chip Fill. 3DIC 2010: 1-5
2000 – 2009
- 2009
- [c2]Keiji Matsumoto, Soichiro Ibaraki, Katsuyuki Sakuma
Thermal resistance measurements of interconnections for a three-dimensional (3D) chip stack. 3DIC 2009: 1-5 - [c1]Yuki Ohara, Akihiro Noriki, Katsuyuki Sakuma
10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. 3DIC 2009: 1-6 - 2008
- [j4]John U. Knickerbocker, Paul S. Andry, Bing Dang, Raymond R. Horton, Mario J. Interrante, Chirag S. Patel, Robert J. Polastre, Katsuyuki Sakuma
Three-dimensional silicon integration. IBM J. Res. Dev. 52(6): 553-569 (2008) - [j3]Bing Dang, Steven L. Wright, Paul S. Andry, Edmund J. Sprogis, Cornelia K. Tsang, M. John Interrante, Bucknell C. Webb, Robert J. Polastre, Raymond R. Horton, Chirag S. Patel, Arun Sharma, J. Zheng, Katsuyuki Sakuma
3D chip stacking with C4 technology. IBM J. Res. Dev. 52(6): 599-609 (2008) - [j2]Katsuyuki Sakuma
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections. IBM J. Res. Dev. 52(6): 611-622 (2008)
1990 – 1999
- 1998
- [j1]Mitsumasa Koyanagi, Hiroyuki Kurino, Kang Wook Lee, Katsuyuki Sakuma
Future system-on-silicon LSI chips. IEEE Micro 18(4): 17-22 (1998)
Coauthor Index
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