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John Reuben
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2020 – today
- 2024
- [c9]John Reuben, Suzanne Lancaster, Dietmar Fey, Stefan Slesazeck:
On-chip READ and WRITE Circuits for Multi-bit Ferroelectric Tunnel Junction Memory. NorCAS 2024: 1-6 - 2023
- [c8]John Reuben, Dietmar Fey, Stefan Slesazeck:
A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories. MOCAST 2023: 1-4 - [c7]Stefan Slesazeck
, Suzanne Lancaster
Hyper Dimensional Computing with Ferroelectric Tunneling Junctions. NANOARCH 2023: 3:1-3:2 - 2022
- [j7]Vijaya Lakshmi
A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1148-1158 (2022) - [j6]Vijaya Lakshmi
Inner Product Computation In-Memory Using Distributed Arithmetic. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4546-4557 (2022) - 2021
- [j5]John Reuben
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1108-1121 (2021) - [c6]Dietmar Fey, John Reuben, Stefan Slesazeck:
Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic. ICECS 2021: 1-6 - [c5]John Reuben
Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles. ISVLSI 2021: 157-163 - 2020
- [c4]John Reuben
A Parallel-friendly Majority Gate to Accelerate In-memory Computation. ASAP 2020: 93-100 - [c3]Dietmar Fey, John Reuben
Direct state transfer in MLC based memristive ReRAM devices for ternary computing. ECCTD 2020: 1-5
2010 – 2019
- 2019
- [c2]John Reuben
A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM. NORCAS 2019: 1-6 - [p1]John Reuben, Nishil Talati, Nimrod Wald, Rotem Ben Hur, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
A Taxonomy and Evaluation Framework for Memristive Logic. Handbook of Memristor Networks 2019: 1065-1099 - 2017
- [c1]John Reuben
Memristive logic: A framework for evaluation and comparison. PATMOS 2017: 1-8 - 2016
- [j4]Kamineni Sumanth Kumar, John Reuben
Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits. J. Circuits Syst. Comput. 25(11): 1650142:1-1650142:17 (2016) - 2014
- [j3]John Reuben
A novel clock generation algorithm for system-on-chip based on least common multiple. Comput. Electr. Eng. 40(7): 2113-2125 (2014) - [j2]V. Mohammed Zackriya
Low Power fractional-n frequency Divider with Improved Resolution. J. Circuits Syst. Comput. 23(8) (2014) - 2013
- [j1]John Reuben
Capacitance driven clock mesh synthesis to minimize skew and power dissipation. IEICE Electron. Express 10(24): 20130850 (2013)
Coauthor Index
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