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Mohsen Hassanpourghadi
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2020 – today
- 2024
- [c11]Mutian Zhu, Mohsen Hassanpourghadi, Qiaochu Zhang, Mike Shuo-Wei Chen, Anthony F. J. Levi, Sandeep Gupta:
A Novel Multi-Objective Optimization Framework for Analog Circuit Customization. DATE 2024: 1-2 - [c10]R. L. Nguyen, A. Mellati, A. Fernandez, A. Iyer, A. Fan, Benjamín T. Reyes, Cindra Abidin, Claudio Nani, D. Albano, F. Ahmad, Fredy Solis, Gabriele Minoia, Geoff Hatcher, M. Bachu, Marco Garampazzi, Mohsen Hassanpourghadi, N. Fan, P. Prabha, S. Fan, S. Ho, T. Dusatko, Tzu-Fan Wu, W. Elsharkasy, Z. Sun, S. Jantzi, L. Tse:
18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET. ISSCC 2024: 344-346 - 2022
- [j6]Juzheng Liu
, Mohsen Hassanpourghadi
A 10-GS/s 8-bit 2850-μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC. IEEE J. Solid State Circuits 57(12): 3757-3767 (2022) - [c9]Shiyu Su, Qiaochu Zhang
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. ASP-DAC 2022: 100-107 - [c8]Shiyu Su, Qiaochu Zhang
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. ASP-DAC 2022: 526-531 - [c7]Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen:
A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology. ISSCC 2022: 160-162 - 2021
- [j5]Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen:
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis. ACM Trans. Design Autom. Electr. Syst. 26(5): 38:1-38:22 (2021) - [c6]Mohsen Hassanpourghadi, Shiyu Su, Rezwan A. Rasul, Juzheng Liu, Qiaochu Zhang
Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling. DAC 2021: 505-510 - [c5]Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD 2021: 1-9 - [i2]Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen:
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. CoRR abs/2112.07824 (2021) - [i1]Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen:
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. CoRR abs/2112.07825 (2021) - 2020
- [c4]Juzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang
Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. ICCAD 2020: 119:1-119:9
2010 – 2019
- 2019
- [c3]Mohsen Hassanpourghadi, Mike Shuo-Wei Chen:
A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells. CICC 2019: 1-4 - 2018
- [j4]Jae-Won Nam
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation. IEEE J. Solid State Circuits 53(6): 1765-1779 (2018) - 2017
- [j3]Mohsen Hassanpourghadi
A 6-b, 800-MS/s, 3.62-mW Nyquist Rate AC-Coupled VCO-Based ADC in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(6): 1354-1367 (2017) - 2016
- [c2]Jae-Won Nam
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. VLSI Circuits 2016: 1-2 - 2014
- [j2]Mohsen Hassanpourghadi, Milad Zamani
A low-power low-offset dynamic comparator for analog to digital converters. Microelectron. J. 45(2): 256-262 (2014) - 2013
- [j1]Mohsen Hassanpourghadi, Mohammad Sharifkhani:
Fast Static Characterization of Residual-Based ADCs. IEEE Trans. Circuits Syst. II Express Briefs 60-II(11): 746-750 (2013) - [c1]Mohsen Hassanpourghadi, Mohammad Sharifkhani:
Step response analysis of third order OpAmps With slew-rate. VLSI-SoC 2013: 62-63
Coauthor Index
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last updated on 2024-10-01 20:48 CEST by the dblp team
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