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Nandakishor Yadav
Person information
- affiliation: Indian Institute of Technology Indore, India
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2020 – today
- 2023
- [j8]Medeswara Rao Kondamudi, Somya Ranjan Sahoo, Lokesh Chouhan, Nandakishor Yadav:
A comprehensive survey of fake news in social networks: Attributes, features, and detection approaches. J. King Saud Univ. Comput. Inf. Sci. 35(6): 101571 (2023) - 2022
- [j7]Nand Kishor Yadav
, Mukesh Saraswat
A novel fuzzy clustering based method for image segmentation in RGB-D images. Eng. Appl. Artif. Intell. 111: 104709 (2022) - 2020
- [j6]Shuai Li
A Novel FPGA Accelerator Design for Real-Time and Ultra-Low Power Deep Convolutional Neural Networks Compared With Titan X GPU. IEEE Access 8: 105455-105471 (2020)
2010 – 2019
- 2019
- [j5]Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Nand Kishor Yadav, Santosh Kumar Vishvakarma
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM. Circuits Syst. Signal Process. 38(4): 1482-1505 (2019) - [j4]Ambika Prasad Shah
SUBHDIP: process variations tolerant subthreshold Darlington pair-based NBTI sensor circuit. IET Comput. Digit. Tech. 13(3): 243-249 (2019) - 2018
- [j3]Ambika Prasad Shah
An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells. Microelectron. Reliab. 87: 15-23 (2018) - 2017
- [c7]Ambika Prasad Shah
LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits. VDAT 2017: 441-451 - 2016
- [c6]Shraddha Thakre, Ankur Beohar, Vikas Vijayvargiya, Nandakishor Yadav
Investigation of DC Characteristic on DG-Tunnel FET with High-K Dielectric Using Distinct Device Parameter. iNIS 2016: 124-128 - [c5]Nandakishor Yadav
Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k Spacer FinFET. iNIS 2016: 264-267 - 2015
- [j2]Nandakishor Yadav
New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET. J. Low Power Electron. 11(1): 49-62 (2015) - [j1]Nandakishor Yadav
A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM. Microelectron. Reliab. 55(8): 1131-1143 (2015) - 2014
- [c4]Nandakishor Yadav
NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique. NANOARCH 2014: 122-128 - [c3]Ekta Prajapati, Nandakishor Yadav
Operation-aware assist circuit design for improved write performance of FinFET based SRAM. VDAT 2014: 1-6 - [c2]Nandakishor Yadav
A New Sensitivity-Driven Process Variation Aware Self-Repairing Low-Power SRAM Design. VLSID 2014: 116-121 - 2013
- [c1]Nandakishor Yadav, Sunil Dutt, Manisha Pattanaik, G. K. Sharma:
Double-gate FinFET process variation aware 10T SRAM cell topology design and analysis. ECCTD 2013: 1-4
Coauthor Index
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