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Romesh Kumar Nandwana
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2020 – today
- 2023
- [c14]Kadaba Lakshmikumar, Alexander Kurylak, Romesh Kumar Nandwana, Bibhu Das, Joe Pampanin, Mike Brubaker, Pavan Kumar Hanumolu:
A 7 pA/$\surd\text{Hz}$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS. ISSCC 2023: 206-207 - 2022
- [j12]Abhishek Bhat
, Romesh Kumar Nandwana, Kadaba Lakshmikumar
An Interference Suppression Technique for Millimeter-Wave LC VCOs Using a Multiport Coupled Inductor. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 919-923 (2022) - [c13]Kadaba R. Lakshmikumar, Alexander Kurylak, Romesh Kumar Nandwana, Bibhu Das, Joe Pampanin, Vito Boccuzzi, Pavan Kumar Hanumolu:
High-Performance CMOS TIA for Data Center Optical Interconnects. BCICTS 2022: 9-16 - 2021
- [j11]Mostafa Gamal Ahmed
A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling. IEEE J. Solid State Circuits 56(9): 2795-2803 (2021)
2010 – 2019
- 2019
- [j10]Ahmed Elkholy
A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler. IEEE J. Solid State Circuits 54(7): 2049-2058 (2019) - [j9]Kadaba Lakshmikumar
A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links. IEEE J. Solid State Circuits 54(11): 3180-3190 (2019) - 2017
- [b1]Romesh Kumar Nandwana:
Clock multiplication techniques for high-speed I/Os. University of Illinois Urbana-Champaign, USA, 2017 - [j8]Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu:
A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS. IEEE J. Solid State Circuits 52(1): 8-20 (2017) - [j7]Saurabh Saxena
A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. IEEE J. Solid State Circuits 52(5): 1399-1411 (2017) - [j6]Mrunmay Talegaonkar
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits 52(9): 2306-2320 (2017) - [j5]Romesh Kumar Nandwana, Saurabh Saxena
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 283-295 (2017) - [c12]Braedon Salz, Mrunmay Talegaonkar, Guanghua Shu, Ahmed Elmallah, Romesh Kumar Nandwana, Bibhudatta Sahoo, Pavan Kumar Hanumolu:
A 0.7V time-based inductor for fully integrated low bandwidth filter applications. CICC 2017: 1-4 - [c11]Junheng Zhu, Makrand Mahalley, Guanghua Shu, Woo-Seok Choi, Romesh Kumar Nandwana, Ahmed Elkholy, Bibhudatta Sahoo, Pavan Kumar Hanumolu:
A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS. CICC 2017: 1-4 - [c10]Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu:
8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. ISSCC 2017: 152-153 - [c9]Romesh Kumar Nandwana, Saurabh Saxena
29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. ISSCC 2017: 492-493 - 2016
- [j4]Ahmed Elkholy
A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider. IEEE J. Solid State Circuits 51(8): 1771-1784 (2016) - [c8]Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu:
19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS. ISSCC 2016: 338-340 - [c7]Guanghua Shu, Woo-Seok Choi, Saurabh Saxena
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. ISSCC 2016: 398-399 - 2015
- [j3]Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. IEEE J. Solid State Circuits 50(4): 882-895 (2015) - [j2]Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator. IEEE J. Solid State Circuits 50(12): 2814-2824 (2015) - [c6]Ahmed Elkholy, Saurabh Saxena
A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter. CICC 2015: 1-4 - [c5]Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Ahmad Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS. ISSCC 2015: 1-3 - [c4]Saurabh Saxena
A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. VLSIC 2015: 352- - 2014
- [j1]Saurabh Saxena
A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis. IEEE J. Solid State Circuits 49(8): 1827-1836 (2014) - [c3]Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. VLSIC 2014: 1-2 - [c2]Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC 2014: 1-2 - 2013
- [c1]Saurabh Saxena
A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter. CICC 2013: 1-4
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