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Masaya Kibune
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2010 – 2019
- 2017
- [c17]Masaya Kibune, Michael G. Lee:
Efficient Learning Algorithm Using Compact Data Representation in Neural Networks. ICONIP (2) 2017: 315-324 - 2015
- [j17]Joshua Liang
, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs. IEEE J. Solid State Circuits 50(4): 845-855 (2015) - [j16]Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
A Reference-Less Single-Loop Half-Rate Binary CDR. IEEE J. Solid State Circuits 50(9): 2037-2047 (2015) - [j15]Mohammad Sadegh Jalali, Clifford Ting, Joshua Liang
A 3x blind ADC-based CDR for a 20 dB loss channel. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(6): 1658-1667 (2015) - [c16]Yanfei Chen, Masaya Kibune, Asako Toda, Akinori Hayakawa, Tomoyuki Akiyama, Shigeaki Sekiguchi, Hiroji Ebe, Nobuhiro Imaizumi, Tomoyuki Akahoshi, Suguru Akiyama, Shinsuke Tanaka, Takasi Simoyama, Ken Morito, Takuji Yamamoto, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura:
22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI. ISSCC 2015: 1-3 - [c15]Akinori Hayakawa, Masaya Kibune, Asako Toda, Shinsuke Tanaka, Takasi Simoyama, Yanfei Chen, Tomoyuki Akiyama, Shigekazu Okumura, Takeshi Baba, Tomoyuki Akahoshi, Seiji Ueno, Kazunori Maruyama, Masahiko Imai, Jian Hong Jiang, Pradip Thachile, Tamer Riad, Shigeaki Sekiguchi, Suguru Akiyama, Yu Tanaka, Ken Morito, Daisuke Mizutani, Toshihiko Mori, Takuji Yamamoto, Hiroji Ebe:
A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects. OFC 2015: 1-3 - 2014
- [j14]Ravi Shivnaraine, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset". IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 2129-2138 (2014) - [c14]Clifford Ting, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE. CICC 2014: 1-4 - [c13]Joshua Liang
On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs. VLSIC 2014: 1-2 - 2013
- [j13]Clifford Ting, Joshua Liang
A Blind Baud-Rate ADC-Based CDR. IEEE J. Solid State Circuits 48(12): 3285-3295 (2013) - [c12]Mohammad Sadegh Jalali, Ravi Shivnaraine, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection. CICC 2013: 1-8 - [c11]Clifford Ting, Joshua Liang
A blind baud-rate ADC-based CDR. ISSCC 2013: 122-123 - 2011
- [j12]Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune:
An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS. IEEE J. Solid State Circuits 46(12): 3140-3149 (2011) - [c10]Behrooz Abiri, Ravi Shivnaraine, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune:
A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS. ISSCC 2011: 154-156 - [c9]Shayan Shahramian, Clifford Ting, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune:
A pattern-guided adaptive equalizer in 65nm CMOS. ISSCC 2011: 354-356 - [c8]Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune:
A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS. ISSCC 2011: 436-438 - 2010
- [j11]Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda:
Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. IEICE Trans. Electron. 93-C(3): 295-302 (2010) - [j10]Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda:
A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2456-2462 (2010) - [j9]Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa:
A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS. IEEE J. Solid State Circuits 45(6): 1091-1098 (2010) - [j8]Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker:
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. IEEE J. Solid State Circuits 45(10): 2016-2029 (2010) - [c7]Tina Tahmoureszadeh, Siamak Sarvari, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Masaya Kibune:
A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers. CICC 2010: 1-4 - [c6]Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto:
A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS. ISSCC 2010: 166-167 - [c5]Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh:
A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. ISSCC 2010: 168-169
2000 – 2009
- 2009
- [j7]Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker:
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. IEEE J. Solid State Circuits 44(12): 3580-3589 (2009) - [c4]Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda:
Split capacitor DAC mismatch calibration in successive approximation ADC. CICC 2009: 279-282 - [c3]Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker:
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. ISSCC 2009: 360-361 - 2008
- [c2]Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda:
A dynamic offset control technique for comparator design in scaled CMOS technology. CICC 2008: 495-498 - 2007
- [j6]Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda:
A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS. IEEE J. Solid State Circuits 42(3): 627-636 (2007) - 2006
- [j5]Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa:
Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies. IEICE Trans. Electron. 89-C(3): 300-313 (2006) - [c1]Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda:
A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid. ISSCC 2006: 2102-2111 - 2005
- [j4]Hirohito Higashi, Syunitirou Masaki, Masaya Kibune, Satoshi Matsubara, Takaya Chiba, Yoshiyasu Doi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Hirotaka Tamura:
A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization. IEEE J. Solid State Circuits 40(4): 978-985 (2005) - [j3]Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda:
A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS. IEEE J. Solid State Circuits 40(4): 986-993 (2005) - [j2]Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda:
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE J. Solid State Circuits 40(8): 1680-1687 (2005) - 2003
- [j1]Hideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura:
A CMOS multichannel 10-Gb/s transceiver. IEEE J. Solid State Circuits 38(12): 2094-2100 (2003)
Coauthor Index
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