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François Marc
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2020 – today
- 2022
- [c12]Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng
, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O'Connor, Oskar Baumgartner
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors. VLSI-SoC 2022: 1-2 - 2021
- [c11]Sébastien Fregonese, Chhandak Mukherjee, Holger Rücker, Pascal Chevalier, Gerhard Fischer, Didier Céli, Marina Deng
Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance. BCICTS 2021: 1-7 - 2020
- [c10]Chhandak Mukherjee, Marina Deng
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. VLSI-SOC 2020: 76-81 - [c9]Arnaud Poittevin, Chhandak Mukherjee, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. VLSI-SoC (Selected Papers) 2020: 301-321 - [i1]C. Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu:
3D logic cells design and results based on Vertical NWFET technology including tied compact model. CoRR abs/2005.14039 (2020)
2010 – 2019
- 2019
- [c8]Marine Couret
Impact of SiGe HBT hot-carrier degradation on the broadband amplifier output supply current. ESSDERC 2019: 154-157 - 2018
- [j20]Julien Coutet, François Marc, Flavien Dozolme, Romain Guétard, Aurélien Janvresse, Pierre Lebossé, Antonin Pastre, Jean-Claude Clement:
Influence of temperature of storage, write and read operations on multiple level cells NAND flash memories. Microelectron. Reliab. 88-90: 61-66 (2018) - [j19]Jorgue Daniel Aguirre Morales, François Marc, A. Bensoussan, A. Durier:
Simulation and modelling of long term reliability of digital circuits implemented in FPGA. Microelectron. Reliab. 88-90: 1130-1134 (2018) - [j18]Christopher H. Bennett
Multiscaled Simulation Methodology for Neuro-Inspired Circuits Demonstrated with an Organic Memristor. IEEE Trans. Multi Scale Comput. Syst. 4(4): 822-832 (2018) - 2017
- [j17]Nathalie Labat, François Marc, Hélène Frémont, Marise Bafleur:
Proceedings of the 28th European Symposium on the reliability of electron devices, failure physics and analysis. Microelectron. Reliab. 76-77: 1-5 (2017) - 2016
- [j16]Mohammad Naouss
FPGA LUT delay degradation due to HCI: Experiment and simulation results. Microelectron. Reliab. 64: 31-35 (2016) - [c7]Mohammad Naouss, François Marc:
Modelling delay degradation due to NBTI in FPGA Look-up tables. FPL 2016: 1-4 - 2015
- [j15]Marise Bafleur, Philippe Perdu, François Marc, Hélène Frémont, Nicolas Nolhier:
Editorial. Microelectron. Reliab. 55(9-10): 1269-1270 (2015) - [j14]Mohammad Naouss, François Marc:
Design and implementation of a low cost test bench to assess the reliability of FPGA. Microelectron. Reliab. 55(9-10): 1341-1345 (2015) - 2013
- [j13]Olivier Héron, Clement Bertolini, Chiara Sandionigi, Nicolas Ventroux, François Marc:
On the Simulation of HCI-Induced Variations of IC Timings at High Level. J. Electron. Test. 29(2): 127-141 (2013) - [j12]Nathalie Labat, François Marc:
Editorial. Microelectron. Reliab. 53(9-11): 1169-1170 (2013) - 2012
- [j11]Tushar Gupta, Clement Bertolini, Olivier Héron, Nicolas Ventroux, Thomas Zimmer, François Marc:
Impact of Power Consumption and Temperature on Processor Lifetime Reliability. J. Low Power Electron. 8(1): 83-94 (2012) - [c6]Bertrand Ardouin, Jean-Yves Dupuy, Jean Godin, Virginie Nodjiadjim, Muriel Riet, François Marc, Gilles Amadou Koné, Sudip Ghosh
Advancements on reliability-aware analog circuit design. ESSCIRC 2012: 46-52 - [c5]Clement Bertolini, Olivier Héron, Nicolas Ventroux, François Marc:
Relation between HCI-induced performance degradation and applications in a RISC processor. IOLTS 2012: 67-72 - 2011
- [j10]Nathalie Labat, François Marc:
Editorial. Microelectron. Reliab. 51(9-11): 1423-1424 (2011) - [j9]G. A. Koné, Brice Grandchamp, C. Hainaut, François Marc, Cristell Maneux
Reliability of submicron InGaAs/InP DHBT under thermal and electrical stresses. Microelectron. Reliab. 51(9-11): 1730-1735 (2011) - [j8]Sudip Ghosh
Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design. Microelectron. Reliab. 51(9-11): 1736-1741 (2011) - 2010
- [j7]G. A. Koné, Brice Grandchamp, C. Hainaut, François Marc, Cristell Maneux
Preliminary results of storage accelerated aging test on InP/InGaAs DHBT. Microelectron. Reliab. 50(9-11): 1548-1553 (2010) - [j6]Sudip Ghosh
Thermal aging model of InP/InGaAs/InP DHBT. Microelectron. Reliab. 50(9-11): 1554-1558 (2010) - [c4]Tushar Gupta, Clement Bertolini, Olivier Héron, Nicolas Ventroux, Thomas Zimmer, François Marc:
High Level Power and Energy Exploration Using ArchC. SBAC-PAD 2010: 25-32
2000 – 2009
- 2009
- [j5]Corinne Bestory, François Marc, S. Duzellier, Hervé Levi:
Electrical aging behavioral modeling for reliability analyses of ionizing dose effects on an n-MOS simple current mirror. Microelectron. Reliab. 49(9-11): 946-951 (2009) - 2007
- [j4]Corinne Bestory, François Marc, Hervé Levi:
Statistical analysis during the reliability simulation. Microelectron. Reliab. 47(9-11): 1353-1357 (2007) - 2006
- [c3]Corinne Bestory, François Marc, Hervé Levi, Yves Danto:
Multi-level Modeling of Hot Carrier Injection for Reliability. FDL 2006: 61-68 - 2004
- [j3]Geneviève Duchamp, Frédéric Verdier, Yannick Deshayes, François Marc, Yves Ousten, Yves Danto:
Reliability of Low-Cost PCB Interconnections for Telecommunication Applications. Microelectron. Reliab. 44(9-11): 1299-1304 (2004) - 2003
- [j2]B. Mongellaz, François Marc, Yves Danto:
Ageing simulation of MOSFET circuit using a VHDL-AMS behavioural modelling: an experimental case study. Microelectron. Reliab. 43(9-11): 1513-1518 (2003) - [c2]François Marc, B. Mongellaz, Yves Danto:
Reliability simulation of electronic circuits with VHDL-AMS. FDL 2003: 175-184 - 2002
- [j1]B. Mongellaz, François Marc, Noëlle Milet-Lewis, Yves Danto:
Contribution to ageing simulation of complex analogue circuit using VHDL-AMS behavioural modelling language. Microelectron. Reliab. 42(9-11): 1353-1358 (2002) - 2000
- [c1]Marc Lecouve, Pierre Jarry, Eric Kerherve, Nicolas Boutheiller, François Marc:
Genetic algorithm optimisation for evanescent mode waveguide filter design. ISCAS 2000: 411-414
Coauthor Index
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