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Sheqin Dong
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2020 – today
- 2024
- [j29]Zhenyi Gao, Sheqin Dong, Zhicong Tang, Wenjian Yu:
MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array. ACM Trans. Design Autom. Electr. Syst. 29(6): 1-23 (2024) - [c78]Zhenyi Gao, Sheqin Dong, Zifei Cheng, Wenjian Yu:
MORE-Router+: Multilayer Multi-capacity ORdered Escape Routing via Bus-oriented Layer Assignment. ISQED 2024: 1-7 - 2023
- [c77]Zhenyi Gao, Sheqin Dong, Zhicong Tang, Wenjian Yu:
MC-MCF: A Multi-Capacity Model for Ordered Escape Routing. ISQED 2023: 1-7 - 2020
- [c76]Zhaopo Liao, Sheqin Dong:
A Constraint-Driven Compact Model with Partition Strategy for Ordered Escape Routing. ACM Great Lakes Symposium on VLSI 2020: 393-398
2010 – 2019
- 2018
- [j28]Fengxian Jiao, Sheqin Dong:
Ordered Escape Routing with Consideration of Differential Pair and Blockage. ACM Trans. Design Autom. Electr. Syst. 23(4): 46:1-46:26 (2018) - [c75]Fengxian Jiao, Sheqin Dong, Bei Yu, Bing Li, Ulf Schlichtmann
:
Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips. ISCAS 2018: 1-4 - [c74]Qian Chen, Sheqin Dong:
A Novel Mixed-Size Fixed-Outline Floorplacement Algorithm. ISVLSI 2018: 215-219 - 2017
- [j27]Kan Wang, Sheqin Dong, Fengxian Jiao
TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1089-1102 (2017) - 2016
- [c73]Fengxian Jiao, Sheqin Dong:
Ordered Escape routing for grid pin array based on Min-cost Multi-commodity Flow. ASP-DAC 2016: 384-389 - 2015
- [j26]Sheqin Dong, Jianchang Ao, Fuqi Luo:
Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect Structure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 740-752 (2015) - 2014
- [j25]Kan Wang
Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 571-584 (2014) - [c72]Kan Wang
Post-floorplanning power optimization for MSV-driven application specific NoC design. ISCAS 2014: 994-997 - [i4]Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto:
Network flow-based simultaneous retiming and slack budgeting for low power design. CoRR abs/1402.2460 (2014) - [i3]Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto:
Floorplanning and Topology Generation for Application-Specific Network-on-Chip. CoRR abs/1402.2462 (2014) - [i2]Bei Yu, Sheqin Dong, Satoshi Goto:
Multi-Voltage and Level-Shifter Assignment Driven Floorplanning. CoRR abs/1402.2894 (2014) - [i1]Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto:
Voltage and Level-Shifter Assignment Driven Floorplanning. CoRR abs/1402.3149 (2014) - 2013
- [j24]Wenxu Sheng, Sheqin Dong:
Multi-bend bus-driven floorplanning considering fixed-outline constraints. Integr. 46(2): 142-152 (2013) - [c71]Kan Wang
Power optimization for application-specific 3D network-on-chip with multiple supply voltages. ASP-DAC 2013: 362-367 - [c70]Kan Wang
Escape routing of mixed-pattern signals based on staggered-pin-array PCBs. ISPD 2013: 93-100 - [c69]Jianchang Ao, Sheqin Dong, Song Chen
Delay-driven layer assignment in global routing under multi-tier interconnect structure. ISPD 2013: 101-107 - 2012
- [j23]Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen
Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips. IEICE Trans. Electron. 95-C(4): 534-545 (2012) - [j22]Haiqi Wang, Sheqin Dong, Tao Lin, Song Chen
Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2208-2219 (2012) - [j21]Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, David Z. Pan:
UNISM: Unified Scheduling and Mapping for General Networks on Chip. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1496-1509 (2012) - [c68]Tao Lin, Sheqin Dong, Song Chen
Linear optimal one-sided single-detour algorithm for untangling twisted bus. ASP-DAC 2012: 151-156 - [c67]Kan Wang
Voltage island-driven power optimization for application specific network-on-chip design. ACM Great Lakes Symposium on VLSI 2012: 171-176 - [c66]Kan Wang
Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. ISQED 2012: 129-136 - 2011
- [j20]Kan Wang
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2490-2498 (2011) - [j19]Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto:
Buffer Planning for IP Placement Using Sliced-LFF. VLSI Design 2011: 530851:1-530851:10 (2011) - [c65]Jianchang Ao, Sheqin Dong, Song Chen
Through-Silicon-Via assignment for 3D ICs. ASICON 2011: 353-356 - [c64]Kan Wang
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. ASP-DAC 2011: 261-266 - [c63]Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen
Network flow-based simultaneous retiming and slack budgeting for low power design. ASP-DAC 2011: 473-478 - [c62]Wei Zhong, Bei Yu, Song Chen
Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion. ISQED 2011: 144-149 - [c61]Tao Lin, Sheqin Dong, Song Chen
Novel and efficient min cut based voltage assignment in gate level. ISQED 2011: 150-155 - 2010
- [j18]Xu He, Sheqin Dong, Yuchun Ma:
Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs. Integr. 43(4): 342-352 (2010) - [c60]Bei Yu, Sheqin Dong, Song Chen
Floorplanning and topology generation for application-specific network-on-chip. ASP-DAC 2010: 535-540 - [c59]Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng:
Bus via reduction based on floorplan revising. ACM Great Lakes Symposium on VLSI 2010: 9-14 - [c58]Tao Lin, Sheqin Dong, Bei Yu, Song Chen
A revisit to voltage partitioning problem. ACM Great Lakes Symposium on VLSI 2010: 115-118 - [c57]Wentao Sui, Sheqin Dong, Jinian Bian:
Wirelength-driven force-directed 3D FPGA placement. ACM Great Lakes Symposium on VLSI 2010: 435-440 - [c56]Wenxu Sheng, Sheqin Dong, Yuliang Wu, Satoshi Goto:
Fixed outline multi-bend bus driven floorplanning. ISQED 2010: 632-637
2000 – 2009
- 2009
- [j17]Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto:
Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(9): 2283-2294 (2009) - [j16]Bei Yu, Sheqin Dong, Song Chen
Voltage and Level-Shifter Assignment Driven Floorplanning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 2990-2997 (2009) - [c55]Bei Yu, Sheqin Dong, Satoshi Goto, Song Chen
Voltage-island driven floorplanning considering level-shifter positions. ACM Great Lakes Symposium on VLSI 2009: 51-56 - [c54]Sheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto:
Buffer Planning for 3D ICs. ISCAS 2009: 1735-1738 - [c53]Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong:
Simultaneous buffer and interlayer via planning for 3D floorplanning. ISQED 2009: 740-745 - [c52]Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto:
Integrated interlayer via planning and pin assignment for 3D ICs. SLIP 2009: 99-104 - 2008
- [j15]Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto:
Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(6): 1478-1487 (2008) - [j14]Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto:
Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(9): 2456-2464 (2008) - [c51]Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong:
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC 2008: 209-212 - [c50]Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto:
Symmetry constraint based on mismatch analysis for analog layout in SOI technology. ASP-DAC 2008: 772-775 - [c49]Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto:
Cache miss reduction through hardware-assisted loop optimization. CSCWD 2008: 129-134 - [c48]Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto:
HyMacs: hybrid memory access optimization based on custom-instruction scheduling. ACM Great Lakes Symposium on VLSI 2008: 89-94 - [c47]Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng:
A novel fixed-outline floorplanner with zero deadspace for hierarchical design. ICCAD 2008: 16-23 - [c46]Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto:
Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. ISQED 2008: 321-324 - 2007
- [j13]Yaoguang Wei, Sheqin Dong, Xianlong Hong:
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. Integr. 40(4): 406-419 (2007) - [c45]Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong:
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. ASP-DAC 2007: 191-196 - [c44]Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou:
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC 2007: 920-925 - [c43]Kang Zhao, Jinian Bian, Sheqin Dong:
A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. CSCWD 2007: 121-126 - [c42]Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong:
An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI 2007: 564-569 - [c41]Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma:
A Fast 3D-BSG Algorithm for 3D Packing Problem. ISCAS 2007: 2044-2047 - [c40]Hongjie Bai, Sheqin Dong, Xianlong Hong:
Congestion Driven Buffer Planning for X-Architecture. ISQED 2007: 835-840 - [c39]Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong:
Interconnect Power Optimization Based on Timing Analysis. ISVLSI 2007: 119-124 - [c38]Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma:
An accurate and efficient probabilistic congestion estimation model in x architecture. SLIP 2007: 25-32 - 2006
- [j12]Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. 21(6): 922-926 (2006) - [j11]Song Chen
VLSI Block Placement With Alignment Constraints. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 622-626 (2006) - [c37]Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma:
A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. APCCAS 2006: 792-795 - [c36]Di Long, Xianlong Hong, Sheqin Dong:
Signal-path driven partition and placement for analog circuit. ASP-DAC 2006: 694-699 - [c35]Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen:
Buffer planning based on block exchanging. ISCAS 2006 - [c34]Sheqin Dong, Shuyi Zheng, Xianlong Hong:
Floorplanning for 2.5-D system integration using multi-layer-BSG structure. ISCAS 2006 - [c33]Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu:
On handling the fixed-outline constraints of floorplanning using less flexibility first principles. ISCAS 2006 - [c32]Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong:
A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle. JCIS 2006 - [c31]Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong:
Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study. JCIS 2006 - [c30]Sheqin Dong, Rensheng Wang, Fan Guo, Jun Yuan, Xianlong Hong:
Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree. JCIS 2006 - [c29]Kang Zhao, Jinian Bian, Sheqin Dong:
A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization. JCIS 2006 - 2005
- [j10]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen
Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 609-621 (2005) - [c28]Renshen Wang, Sheqin Dong, Xianlong Hong:
An improved P-admissible floorplan representation based on Corner Block List. ASP-DAC 2005: 1115-1118 - [c27]Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu:
LFF algorithm for heterogeneous FPGA floorplanning. ASP-DAC 2005: 1123-1126 - [c26]Rong Liu, Sheqin Dong, Xianlong Hong:
An efficient algorithm to fixed-outline floorplanning based on instance augmentation. CAD/Graphics 2005: 6 - [c25]Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen
A New Buffer Planning Algorithm Based on Room Resizing. EUC 2005: 291-299 - [c24]Rong Liu, Sheqin Dong, Xianlong Hong:
Fixed-outline floorplanning based on common subsequence. ACM Great Lakes Symposium on VLSI 2005: 156-159 - [c23]Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani:
A new approach based on LFF for optimization of dynamic hardware reconfigurations. ISCAS (2) 2005: 1210-1213 - [c22]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) 2005: 1863-1866 - [c21]Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani:
Fixed-outline floorplanning with constraints through instance augmentation. ISCAS (2) 2005: 1883-1886 - [c20]Di Long, Xianlong Hong, Sheqin Dong:
Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. ISCAS (3) 2005: 2999-3002 - [c19]Song Chen
VLSI block placement with alignment constraints based on corner block list. ISCAS (6) 2005: 6222-6225 - [c18]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen
Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED 2005: 213-219 - [c17]Song Chen
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED 2005: 628-633 - 2004
- [j9]Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Corner block list representation and its application with boundary constraints. Sci. China Ser. F Inf. Sci. 47(1): 1-19 (2004) - [j8]Song Chen
A buffer planning algorithm for chip-level floorplanning. Sci. China Ser. F Inf. Sci. 47(6): 763-776 (2004) - [j7]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu:
Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. 19(6): 973-980 (2004) - [j6]Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Corner block list representation and its application to floorplan optimization. IEEE Trans. Circuits Syst. II Express Briefs 51-II(5): 228-233 (2004) - [j5]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. 9(2): 199-211 (2004) - [c16]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm with congestion optimization. ASP-DAC 2004: 615-620 - [c15]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Buffer allocation algorithm with consideration of routing congestion. ASP-DAC 2004: 621-623 - [c14]Sheqin Dong, Zhong Yang, Xianlong Hong, Yuliang Wu:
Module placement based on quadratic programming and rectangle packing using less flexibility first principle. ISCAS (5) 2004: 61-64 - 2003
- [j4]Sheqin Dong, Xianlong Hong, Song Chen, Xin Qi, Ruijie Wang, Jun Gu:
VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3136-3147 (2003) - [j3]Sheqin Dong, Xianlong Hong, Yuliang Wu, Jun Gu:
Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle. J. Comput. Sci. Technol. 18(6): 739-746 (2003) - [c13]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm based on dead space redistribution. ASP-DAC 2003: 435-438 - [c12]Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu:
VLSI module placement with pre-placed modules and considering congestion using solution space smoothing. ASP-DAC 2003: 741-744 - [c11]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC 2003: 806-811 - [c10]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu:
Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) 2003: 493-496 - [c9]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) 2003: 708-711 - [c8]Rui Liu, Sheqin Dong, Xianlong Hong, Di Long, Jun Gu:
Algorithms for analog VLSI 2D stack generation and block merging. ISCAS (4) 2003: 716-719 - [c7]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
An integrated floorplanning with an efficient buffer planning algorithm. ISPD 2003: 136-142 - 2002
- [j2]Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai:
An Optimum Placement Search Algorithm Based on Extended Corner Block List. J. Comput. Sci. Technol. 17(6): 699-707 (2002) - [c6]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. ASP-DAC/VLSI Design 2002: 387-392 - 2001
- [j1]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with abutment constraints based on corner block list. Integr. 31(1): 65-77 (2001) - [c5]Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC 2001: 509-514 - [c4]Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu:
VLSI block placement using less flexibility first principles. ASP-DAC 2001: 601-604 - [c3]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC 2001: 770-775 - [c2]Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
ECBL: an extended corner block list with solution space including optimum placement. ISPD 2001: 150-155 - 2000
- [c1]Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. ICCAD 2000: 8-12
Coauthor Index
[j20] [c64] [c54] [c53] [c52] [c51] [c50] [j13] [c45] [c44] [c42] [c41] [c40] [c39] [c38] [j12] [j11] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j10] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [j9] [j8] [j7] [j6] [j5] [c16] [c15] [c14] [j4] [j3] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [j2] [c6] [j1] [c5] [c4] [c3] [c1]
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