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Integration, Volume 30
Volume 30, Number 1, November 2000
- Wai-Kei Mak, D. F. Wong
:
A fast hypergraph min-cut algorithm for circuit partitioning. 1-11 - Alejandro F. González, Pinaki Mazumder:
Redundant arithmetic, algorithms and implementations. 13-53 - Hasan Ymeri, Bart Nauwelaers
Computation of capacitance matrix for integrated circuit interconnects using semi-analytic Green's function method. 55-63 - Dimitri Kagaris, Spyros Tragoudas, Amitava Majumdar:
Test-set partitioning for multi-weighted random LFSRs. 65-75 - Dominique Lavenier:
An FPGA systolic array using pseudo-random bit generators for computing Goldbach partitions. 77-89 - George Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas
Management of charge pump circuits. 91-101
Volume 30, Number 2, October 2001
- Scott C. Smith, Ronald F. DeMara
Delay-insensitive gate-level pipelining. 103-131 - Hasan Ymeri, Bart Nauwelaers
Frequency-dependent mutual resistance and inductance formulas for coupled IC interconnects on an Si-SiO2 substrate. 133-141 - Xiaoping Tang, D. F. Wong
Network flow based buffer planning. 143-155 - Soumen Maity, Bimal K. Roy, Amiya Nayak
Enumerating catastrophic fault patterns in VLSI arrays with both uni- and bidirectional links. 157-168 - Kiamal Z. Pekmestzi, Nikos K. Moshopoulos:
A bit-interleaved systolic architecture for a high-speed RSA system. 169-175
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