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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 2
Volume 2, Number 1, January 1983
- Ronald A. Rohrer:
Editorial. 1 - M. Simard-Normandin:
Channel Length Dependence of the Body-Factor Effect in NMOS Devices. 2-4 - Louis J. Hafer, Alice C. Parker:
A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic. 4-18 - Sung-Mo Kang, Robert H. Krambeck, Hung-Fai Stephen Law, Alexander D. Lopez:
Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design. 18-29 - Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa:
On the Layering Problem of Multilayer PWB Wiring. 30-38 - Kazuhiro Ueda, Tsutomu Komatsubara, Tsutomu Hosaka:
A Parallel Processing Approach for Logic Module Placement. 39-47 - G. I. Serhan, Swei-Yam Yu:
A Simple Charge-Based Model for MOS Transistor Capacitances: A New Production Tool. 48-51
Volume 2, Number 2, April 1983
- Dwight D. Hill:
Edisim: A Graphical Simulator Interface for LSI Design. 57-61 - Yuh-Zen Liao, Chak-Kuen Wong:
An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints. 62-69 - Takashi Watanabe, Makoto Endo, Norio Miyahara:
A New Automatic Logic Interconnection Verification System for VLSI Design. 70-82 - Miron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon:
A Logic Simulation Machine. 82-94 - Donald E. Thomas, Gary W. Leive:
Automating Technology Relative Logic Synthesis and Module Selection. 94-105 - D. B. Estreich:
A Simulation Model for Schottky Diodes in GaAs Integrated Circuits. 106-111 - Richard C. Jaeger, Fritz H. Gaensslen, Sherra E. Diehl:
An Efficient Numerical Algorithm for Simulation of MOS Capacitance. 111-116 - Chet A. Palesko, Lex A. Akers:
Logic Partitioning for Minimizing Gate Arrays. 117-121 - Takeshi Shima, Hisashi Yamada, Ryo Luong Mo Dang:
Table Look-Up MOSFET Modeling System Using a 2-D Device Simulator and Monotonic Piecewise Cubic Interpolation. 121-126
Volume 2, Number 3, July 1983
- Takeshi Tokuda, Kaoru Okazaki, Kazuhiro Sakashita, Isao Ohkura, Tatsuya Enomoto:
Delay-Time Modeling for ED MOS Logic LSI. 129-134 - Donald E. Thomas, John A. Nestor:
Defining and Implementing a Multilevel Design Representation with Simulation Applications. 135-145 - Mark Horowitz, Robert W. Dutton:
Resistance Extraction from Mask Layout Data. 145-150 - Giovanni De Micheli, Alberto L. Sangiovanni-Vincentelli:
Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications. 151-167 - Giovanni De Micheli, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits. 167-180 - Dale E. Hocevar, Michael R. Lightner, Timothy N. Trick:
A Study of Variance Reduction Techniques for Estimating Circuit Yields. 180-192 - Dundar Dumlugol, Hugo De Man, Piet Stevens, Guido G. Schrooten:
Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling. 193-202 - Jorge Rubinstein, Paul Penfield Jr., Mark A. Horowitz:
Signal Delay in RC Tree Networks. 202-211
Volume 2, Number 4, October 1983
- Ernest S. Kuh:
Editorial: Routing in Microelectronics. 213-214 - Mario P. Vecchi, Scott Kirkpatrick:
Global Wiring by Simulated Annealing. 215-222 - Michael Burstein, Richard N. Pelavin:
Hierarchical Wire Routing. 223-234 - Chi-Ping Hsu:
Minimum-Via Topological Routing. 235-246 - Malgorzata Marek-Sadowska, Tom Tsan-Kuo Tarng:
Single-Layer Routing for VLSI: Analysis and Algorithms. 246-259 - Harold W. Carter, Melvin A. Breuer:
Efficient Single-Layer Routing Along a Line of Points. 259-266 - Isao Shirakawa, Shin Futagami:
A Rerouting Scheme for Single-Layer Printed Wiring Boards. 267-271 - Hans-Jürgen Rothermel, Dieter A. Mlynski:
Automatic Variable-Width Routing for VLSI. 271-284 - Sieji Kimura, Noboru Kubo, Toru Chiba, Ikuo Nishioka:
An Automatic Routing Scheme for General Cell LSI. 285-292 - Yoji Kajitani:
Order of Channels for Safe Routing and Optimal Compaction of Routing Area. 293-300 - B. S. Ting, Bou Nin Tien:
Routing Techniques for Gate Array. 301-312 - Shuji Tsukiyama, Ikuo Harada, Masahiro Fukui, Isao Shirakawa:
A New Global Router for Gate Array LSIsi. 313-321
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