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28th SoCC 2015: Beijing, China
- 28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015. IEEE 2015, ISBN 978-1-4673-9094-1
- Chris Rowen:
"Five Forces Shaping the Silicon World: Advanced sensing and intelligence in IoT and vision". - Gavin Stark:
"Unicorns and centaurs: Architecting SOCs for software defined networking". - Jason Cong:
"High-level synthesis and beyond - From datacenters to IoTs". - Rui Hou:
"Venice: A cost-effective architecture for datacenter servers". - Bill Ma, Qinjin Huang
, Fengqi Yu:
A 12-bit 1.74-mW 20-MS/s DAC with resistor-string and current-steering hybrid architecture. 1-6 - Koki Igawa, Youhua Shi
A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. 7-12 - Xabier Iturbe
Designing a SoC to control the next-generation space exploration flight science instruments. 13-18 - Jun Guo, Peng Liu, Weidong Wang, Jicheng Chen, Yingtao Jiang:
A 20 GHz high speed, low jitter, high accuracy and wide correction range duty cycle corrector. 19-24 - Yung-Hui Chung, Cheng-Hsun Tsai, Hsuan-Chin Yeh:
A 5-b 1-GS/s 2.7-mW binary-search ADC in 90nm digital CMOS. 25-29 - Ting-Li Chu, Wen-Yu Chu, Yasuyoshi Fujii, Chorng-Sii Hwang:
All-digital deskew buffer using a hybrid control scheme. 30-34 - László Szilágyi, Ronny Henker, Frank Ellinger:
A 0.68 pJ/bit inductor-less optical receiver for 20 Gbps with 0.0025 mm2 area in 28 nm CMOS. 35-39 - Seok Min Jung, Janet Meiling Roveda:
A 320MHz-2.56GHz low jitter phase-locked loop with adaptive-bandwidth technique. 40-43 - Henry Lopez Davila
A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems. 44-48 - Nisha Gupta, A. R. Aravinth Kumar, Ashudeb Dutta, Shiv Govind Singh:
A 1.2V wide-band reconfigurable mixer for wireless application in 65nm CMOS technology. 49-52 - Yue Zhao, Hosoon Shin, Hai-Bao Chen, Sheldon X.-D. Tan, Guoyong Shi, Xin Li:
Statistical rare event analysis using smart sampling and parameter guidance. 53-58 - Xin Yang, Sakir Sezer:
Per-flow state management technique for high-speed networks. 59-63 - Kratika Garg, Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan:
KnapSim - Run-time efficient hardware-software partitioning technique for FPGAs. 64-69 - Yanjie Gu, Guoyong Shi:
Optimal realization of switched-capacitor circuits by symbolic analysis. 70-73 - Islam Mostafa, Ayman H. Ismail
A tunable inverter-based, low-voltage OTA for continuous-time ΣΔ ADC. 74-77 - To-Po Wang, Shih-Hua Chiang:
A high-gain low-power low-noise-figure differential CMOS LNA with 33% current-reused negative-conductance accommodation structure. 78-81 - Evan K. Jorgensen, P. R. Mukund:
A comparative study of multi-GHz LCVCOs designed in 28nm CMOS technology. 82-87 - Josef Dobes, Jan Míchal, Jakub Popp, Martin Grábner, Frantisek Vejrazka, Jakub Kakona:
Multi-objective optimization of a low-noise antenna amplifier for multi-constellation satellite-navigation receivers. 88-93 - Yanqi Zheng, Marco Ho
A digital-control sensorless current-mode boost converter with non-zero error bin compensation and seamless mode transition. 94-99 - Xiao-bo Jiang, Xue-qing Tan, Wei-pei Huang:
Novel ECC structure and evaluation method for NAND flash memory. 100-104 - Gaurav Narang, Alexander Fell
Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems. 105-110 - Hsin-Ping Yang, Hsiao-Chi Hsieh, Sheng-Hsiang Chang, Sao-Jie Chen
An improved distributed video coding with low-complexity motion estimation at encoder. 111-114 - Shufan Yang
Modelling visual attention towards embodiment cognition on a reconfigurable and programmable system. 115-120 - Hiroyuki Yamauchi
A filter design to increase accuracy of Lucy-Richardson deconvolution for analyzing RTN mixtures effects on VLSI reliability margin. 121-126 - Jai Narayan Tripathi
Analysis of a serial link for power supply induced jitter. 127-130 - Jian Hu, Tun Li, Sikun Li:
Formal equivalence checking between SLM and RTL descriptions. 131-136 - Mahnaz Mohammadi, Rohit Ronge, Jayesh Ramesh Chandiramani, Soumitra Kumar Nandy:
An accelerator for classification using radial basis function neural network. 137-142 - Abdullah M. Zyarah
Reconfigurable hardware architecture of the spatial pooler for hierarchical temporal memory. 143-153 - Farshad Moradi
Low-voltage 9T FinFETSRAM cell for low-power applications. 149-153 - Jie Jin, Lingling Sun, Feng Guo, Xiaojun Wang
Low power design for on-chip networking processing system. 154-159 - Pengzhan Yan, Shixiong Jiang, Ramalingam Sridhar:
A high throughput router with a novel switch allocator for network on chip. 160-163 - Xiaofan Zhang, Masoumeh Ebrahimi, Letian Huang, Guangjun Li:
Fault-resilient routing unit in NoCs. 164-169 - Taehoon Kim, Sunkwon Kim, Jong-Kwan Woo, Hyongmin Lee, Suhwan Kim:
A 9-bit, 110-MS/s pipelined-SAR ADC using time-interleaved technique with shared comparator. 170-174 - Han Zhou, Xiaoyan Gui, Peng Gao:
Design of a 12-bit 0.83 MS/s SAR ADC for an IPMI SoC. 175-179 - Ricardo Santos, Renan A. Marks, Rafael Alves, Felipe Araujo, Renato Santos
Instruction decoders based on pattern factorization. 180-185 - Xiang Wang, Lin Li, Longbin Zhang, Weike Wang
A multi-level collaboration low-power design based on embedded system. 186-190 - Alexander Fell
A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address. 191-196 - Suresh Koyada, Abhilash Karnatakam Nagabhushana, Stefan Leitner, Haibo Wang:
An A-SAR ADC circuit with adaptive auxiliary comparison scheme. 197-202 - Ujjwal Gupta, Sankalp Jain, Ümit Y. Ogras
Can systems extend to polymer? SoP architecture design and challenges. 203-208 - Santhosh Kumar Rethinagiri, Oscar Palomar
FAcET: Fast and accurate power/energy estimation tool for CPU-GPU platforms at architectural-level. 209-214 - Hooman Farkhani, Ali Peiravi, Jens Kargaard Madsen, Farshad Moradi
Symmetric write operation for 1T-1MTJ STT-RAM cells using negative bitline technique. 215-220 - Shunbin Li, Peng Liu, Weidong Wang, Xing Fang, Dong Wu, Xianghui Xie:
A PAM-4 adaptive analog equalizer with decoupling control loops for 25-Gb/s CMOS serial-link receiver. 221-226 - Yujin Park, Han Yang
Low noise output stage for oversampling audio DAC. 227-230 - Wuguang Wang, Rulin Huang, Guoquan Sun, Weijun Mao, Xiaolei Zhu:
A digital background calibration technique for split DAC based SAR ADC by using redundant cycle. 231-234 - Yuxiang Huan, Ning Ma, Stefan Blixt, Zhuo Zou, Li-Rong Zheng:
A 61 μA/MHz reconfigurable application-specific processor and system-on-chip for Internet-of-Things. 235-239 - Zhijian Lu, Hongyi Wang, Syed Roomi Naqvi, Houqiang Fu
A point of care electrochemical impedance spectroscopy device. 240-244 - Chun-Ying Huang, Po-Tsang Huang, Chih-Chao Yang, Ching-Te Chuang, Wei Hwang:
Energy-efficient gas recognition system with event-driven power control. 245-250 - Zhenzhi Wu, Dake Liu, Xiaoyang Li:
Loop acceleration and instruction repeat support for application specific instruction-set processors. 251-256 - Jui-Hung Chen, Yung-Chih Chen, Wan-Chen Weng, Ching-Yi Huang, Chun-Yao Wang:
Synthesis and verification of cyclic combinational circuits. 257-262 - Koki Ito, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
Partitioning-based multiplexer network synthesis for field-data extractors. 263-268 - Zhou Jiang, Dong Xiang, Kele Shen:
A scan segmentation architecture for power controllability and reduction. 269-274 - Limin Xiao, Zhenxue He, Li Ruan, Rong Zhang, Tongsheng Xia, Xiang Wang:
Optimization of best polarity searching for mixed polarity reed-muller logic circuit. 275-280 - Wen-Chung Tsai, Hsiao-En Lin, Ying-Cherng Lan, Sao-Jie Chen
A novel flow fluidity meter for BiNoC bandwidth resource allocation. 281-286 - Nasim Nasirian, Magdy A. Bayoumi:
Low-latency power-efficient adaptive router design for network-on-chip. 287-291 - Pengzhan Yan, Shixiong Jiang, Ramalingam Sridhar:
A novel fault-tolerant router architecture for network-on-chip reconfiguration. 292-297 - Soumyajit Poddar
Adaptive CDMA based multicast method for photonic networks on chip. 298-303 - Vaibhav Verma
A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology. 304-309 - Ramandeep Kaur, Alexander Fell
A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI. 310-315 - Anil Kumar Gundu, Mohammad S. Hashmi
Statistical analysis and parametric yield estimation of standard 6T SRAM cell for different capacities. 316-321 - Keissy Guerra Perez, Sandra Scott-Hayward, Xin Yang, Sakir Sezer:
Memory cost analysis for OpenFlow multiple table lookup. 322-327 - Nagaveni Vamsi, Pramod Kaddi, Ashudeb Dutta, Shiv Govind Singh:
A -30 dBm sensitive ultra low power RF energy harvesting front end with an efficiency of 70.1% at -22 dBm. 328-332 - Dongliang Chen, Xin Wang, Jinhui Wang, Na Gong:
VCAS: Viewing context aware power-efficient mobile video embedded memory. 333-338 - Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications. 339-344 - Shixiong Jiang, Pengzhan Yan, Ramalingam Sridhar:
A high speed and low power content-addressable memory(CAM) using pipelined scheme. 345-349 - Hai (Helen) Li
The evolutionary spintronic technologies and their usage in high performance computing. 350-355 - Tianjian Li, Hao Chen
On microarchitectural modeling for CNFET-based circuits. 356-361 - Chen Wang, Li Jiang, Shiyan Hu, Tianjian Li, Xiaoyao Liang, Naifeng Jing, Weikang Qian:
Timing-driven placement for carbon nanotube circuits. 362-367 - Guangxiang Li, Jianping Guo, Yanqi Zheng, Mo Huang, Dihu Chen:
Cascoded flipped voltage follower based output-capacitorless low-dropout regulator for SoCs. 368-373 - Ahmed M. Ammar
A fully integrated charge sharing active decap scheme for power supply noise suppression. 374-379 - Chia-Tsen Dai, Ming-Dou Ker:
ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC. 380-383 - Liuyan Chen, Qi Cheng, Jianping Guo, Min Chen:
High-PSR CMOS LDO with embedded ripple feedforward and energy-efficient bandwidth extension. 384-389 - Qi Hu, Kejun Wu, Peng Liu:
Exploiting multi-band transmission line interconnects to improve the efficiency of cache coherence in multiprocessor system-on-chip. 390-395 - Ting Kang, Zhaowen Yan, Wei Zhang, Jianwei Wang:
Research on crosstalk issue of through silicon via for 3D integration. 396-400 - Weijun Mao, Liusheng Sun, Junwei Xu, Jiajia Wu, Xiaolei Zhu:
Analysis and design of high performance wireless power delivery using on-chip octagonal inductor in 65-nm CMOS. 401-405 - Jingyan Fu, Ligang Hou, Jinhui Wang, Bo Lu, Wei Zhao, Yang Yang:
A novel thermal-aware structure of TSV cluster. 406-409 - Na Bao, Zhe Jiang, Zhiheng Qi, Wei Zhang:
High-throughput MQ encoder for pass-parallel EBCOT in JPEG2000. 410-414 - Liping Li, Wenyi Zhang:
On the encoding complexity of systematic polar codes. 415-420 - Xiao Liang, Chuan Zhang, Menghui Xu, Shunqing Zhang, Xiaohu You
Efficient stochastic list successive cancellation decoder for polar codes. 421-426 - Yun Chen, Yuanzhou Hu, Yizhi Wang, Xiaoyang Zeng, David Huang
EM independent Gaussian approximate message passing and its application in OFDM impulsive noise mitigation. 427-431
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