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19th IOLTS 2013: Chania, Crete, Greece
- 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), Chania, Crete, Greece, July 8-10, 2013. IEEE 2013, ISBN 978-1-4799-0662-8
- José Rodrigo Azambuja, Gustavo Brown, Fernanda Lima Kastensmidt
, Luigi Carro:
Algorithm transformation methods to reduce software-only fault tolerance techniques' overhead. 1-6 - Michael G. Dimopoulos, Yi Gang, Mounir Benabdenbi, Lorena Anghel
Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip. 7-12 - Anna Vaskova, Marta Portela-García
Hardening of serial communication protocols for potentially critical systems in automotive applications: LIN bus. 13-18 - Ijeoma Anarado, Mohammad Ashraful Anam, Davide Anastasia, Fabio Verdicchio, Yiannis Andreopoulos:
Highly-reliable integer matrix multiplication via numerical packing. 19-24 - W. Prates, Letícia Maria Veiras Bolzani, Gurgen Harutyunyan, A. Davtyan, Fabian Vargas, Yervant Zorian:
Integrating embedded test infrastructure in SRAM cores to detect aging. 25-30 - Katerina Katsarou, Yiorgos Tsiatouhas
NBTI aging tolerance in pipeline based designs NBTI. 31-36 - Gilles Bizot, Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Variability-aware and fault-tolerant self-adaptive applications for many-core chips. 37-42 - Mauricio de Carvalho, Paolo Bernardi
Increasing fault coverage during functional test in the operational phase. 43-48 - Michail Maniatakos
Investigating the limits of AVF analysis in the presence of multiple bit errors. 49-54 - Arkady Bramnik, Andrei Sherban, Norbert Seifert:
Timing vulnerability factors of sequential elements in modern microprocessors. 55-60 - Bao Le, Dipanjan Sengupta, Andreas G. Veneris, Zissis Poulos:
Accelerating post silicon debug of deep electrical faults. 61-66 - Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng:
At-speed BIST for interposer wires supporting on-the-spot diagnosis. 67-72 - Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris:
A failure triage engine based on error trace signature extraction. 73-78 - Oscar Ballan, Paolo Bernardi
A software-based self-test strategy for on-line testing of the scan chain circuitries in embedded microprocessors. 79-84 - Gaurang Upasani, Xavier Vera, Antonio González
Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery. 85-91 - Kedar Karmarkar, Spyros Tragoudas:
Error detection encoding for multi-threshold capture mechanism. 92-97 - Boyang Du
Exploiting the debug interface to support on-line test of control flow errors. 98-103 - Fabian Oboril, Ilias Sagar, Mehdi Baradaran Tahoori:
A-SOFT-AES: Self-adaptive software-implemented fault-tolerance for AES. 104-109 - Loïc Zussa, Jean-Max Dutertre
Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism. 110-115 - Loic Welter, Philippe Dreux, Jean-Michel Portal, Hassen Aziza:
Embedded high-precision frequency-based capacitor measurement system. 116-121 - Suvadeep Banerjee
Real-time checking of linear control systems using analog checksums. 122-127 - SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera:
Perturbation-immune radiation-hardened PLL with a switchable DMR structure. 128-132 - Qais Al-Gayem, Hong Liu, Haroon Khan
Scanning the strength of a test signal to monitor electrode degradation within bio-fluidic microsystems. 133-138 - Adrian Evans, Dan Alexandrescu, Enrico Costenaro, Liang Chen:
Hierarchical RTL-based combinatorial SER estimation. 139-144 - Georgios Tsiligiannis
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. 145-150 - Dan Alexandrescu, Enrico Costenaro, Adrian Evans:
State-aware single event analysis for sequential logic. 151-156 - Julian J. H. Pontes, Ney Calazans
Parity check for m-of-n delay insensitive codes. 157-162 - Alaa Aldin Al Hariri, Fabrice Monteiro, Loïc Siéler
A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes. 163-166 - Shyue-Kung Lu, Ming-Chang Chen, Yen-Chi Chen:
Error-tolerance evaluation and design techniques for motion estimation computing arrays. 167-168 - Manolis Kaliorakis, Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis
Online error detection in multiprocessor chips: A test scheduling study. 169-172 - Mohamed Ben Jrad, Régis Leveugle:
Evaluating a low cost robustness improvement in SRAM-based FPGAs. 173-174 - Brice Ekobo Akoa, Emmanuel Simeu, Fritz Lebowsky:
Video decoder monitoring using non-linear regression. 175-178 - Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
A low-cost input vector monitoring concurrent BIST scheme. 179-180 - Nikos Foutris, Dimitris Gizopoulos, John Kalamatianos, Vilas Sridharan:
Measuring the performance impact of permanent faults in modern microprocessor architectures. 181-184 - Chiara Sandionigi, Olivier Héron, Clement Bertolini, Raphaël David:
When processors get old: Evaluation of BTI and HCI effects on performance and reliability. 185-186 - Nikos Andrikos, Massimo Violante, David Merodio Codinachs:
A fully-automated flow for ITAR-free rad-hard Atmel FPGAs. 187-192 - Enshan Yang, Keheng Huang, Yu Hu, Xiaowei Li, Jian Gong, Hongjin Liu, Bo Liu:
HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs. 193-198 - Stefano Di Carlo
Ef3S: An evaluation framework for flash-based systems. 199-204 - Sebastià A. Bota
Accurate alpha soft error rate evaluation in SRAM memories. 205-209 - Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kostas Tsoumanis, Kiamal Z. Pekmestzi:
A radiation tolerant and self-repair memory cell. 210-215 - Michael Nicolaidis, Panagiota Papavramidou:
Transparent BIST for ECC-based memory repair. 216-223 - Yier Jin
A post-deployment IC trust evaluation architecture. 224-225 - Debdeep Mukhopadhyay:
On-line testing for differential fault attacks in cryptographic circuits. 226-227 - Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A smart test controller for scan chains in secure circuits. 228-229 - Sk Subidh Ali
Scan attack in presence of mode-reset countermeasure. 230-231 - Jeyavijayan Rajendran, Huan Zhang, Ozgur Sinanoglu
High-level synthesis for security and trust. 232-233 - Stefano Di Carlo
Increasing the robustness of CUDA Fermi GPU-based systems. 234-235 - Sotiris Tselonis, Vasilis Dimitsas, Dimitris Gizopoulos:
The functional and performance tolerance of GPUs to permanent faults in registers. 236-239 - Hans-Joachim Wunderlich, Claus Braun, Sebastian Halder:
Efficacy and efficiency of algorithm-based fault-tolerance on GPUs. 240-243 - Paolo Rech
Experimental evaluation of GPUs radiation sensitivity and algorithm-based fault tolerance efficiency. 244-247 - Georgios Karakonstantis, David Atienza, Andy Burg:
Exploiting application resiliency for energy-efficient and adequately-reliable operation. 249 - Kwanyeob Chae, Saibal Mukhopadhyay:
Error resilient logic circuits under dynamic variations. 250 - Georgios Panagopoulos, Phillipp Riess, Peter Baumgartner:
Challenges of RF and mixed signal design under process variability. 251 - Anand Raghunathan, Kaushik Roy:
Approximate computing: Energy-efficient computing with good-enough results. 258
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