default search action
ICCD 2014: Seoul, South Korea
- 32nd IEEE International Conference on Computer Design, ICCD 2014, Seoul, South Korea, October 19-22, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-6492-5
Memory Architecture
- Ishan G. Thakkar, Sudeep Pasricha:
3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time. 1-7 - Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu:
The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost. 8-15 - Mengying Zhao, Liang Shi, Chengmo Yang, Chun Jason Xue
:
Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memory. 16-21 - Jue Wang, Xiangyu Dong, Yuan Xie:
ProactiveDRAM: A DRAM-initiated retention management scheme. 22-27 - Wei Wei, Dejun Jiang, Jin Xiong, Mingyu Chen:
HAP: Hybrid-memory-Aware Partition in shared Last-Level Cache. 28-35
Logic and Circuit Design in Advanced Technologies
- Manish Rana, Ramon Canal:
REEM: Failure/non-failure region estimation method for SRAM yield analysis. 36-41 - Levent Aksoy
Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA. 42-47 - Hang Zhang, Wei Zhang, John C. Lach:
A low-power accuracy-configurable floating point multiplier. 48-54 - Viacheslav V. Fedorov, Monther Abusultan, Sunil P. Khatri:
An area-efficient Ternary CAM design using floating gate transistors. 55-60 - Andreas Steininger
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. 61-67
Best Paper Session
- Shrikanth Ganapathy, Ramon Canal, Antonio González
iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches. 68-74 - Michael J. Lyons, Gu-Yeon Wei, David M. Brooks:
Multi-accelerator system development with the ShrinkFit acceleration framework. 75-82 - Seokin Hong, Jongmin Lee, Soontae Kim
Ternary cache: Three-valued MLC STT-RAM caches. 83-89 - Jaehyeong Sim
Timing error masking by exploiting operand value locality in SIMD architecture. 90-96 - Zhongdong Qi, Yici Cai, Qiang Zhou:
Accurate prediction of detailed routing congestion using supervised data learning. 97-103
Caches/Mapping
- Pritam Majumder, T. Venkata Kalyan
SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache. 104-109 - Akhil Arunkumar, Carole-Jean Wu:
ReMAP: Reuse and memory access cost aware eviction policy for last level cache management. 110-117 - Karthikeyan Dayalan, Meltem Ozsoy, Dmitry V. Ponomarev:
Dynamic associative caches: Reducing dynamic energy of first level caches. 118-124 - Cheng-Chieh Huang, Vijay Nagarajan:
Increasing cache capacity via critical-words-only cache. 125-132 - Jianxing Wang, Pooja Roy, Weng-Fai Wong
Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration. 133-138
Special Session A: The Semiconductor Roadmap 2.0
- Juan Antonio Carballo, Wei-Ting Jonas Chan, Paolo A. Gargini, Andrew B. Kahng, Siddhartha Nath:
ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap. 139-146 - Mustafa Badaroglu, Kwok Ng, Mehdi Salmani Jelodar, SungGeun Kim, Gerhard Klimeck
More Moore landscape for system readiness - ITRS2.0 requirements. 147-152 - Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath, Ichiro Yamamoto:
The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap. 153-160 - Gary Smith:
Updates of the ITRS design cost and power models. 161-165
Reliability, Security, Test and Verification
- Cristiana Bolchini
A lightweight and open-source framework for the lifetime estimation of multicore systems. 166-172 - Darshana Jayasinghe, Roshan G. Ragel, Jude Angelo Ambrose, Aleksandar Ignjatovic, Sri Parameswaran
Advanced modes in AES: Are they safe from power analysis based side channel attacks? 173-180 - Ran Wang, Krishnendu Chakrabarty
Built-in self-test for interposer-based 2.5D ICs. 181-188 - Bei Zhang, Vishwani D. Agrawal:
An optimized diagnostic procedure for pre-bond TSV defects. 189-194 - Vidura Wijayasekara, Sudarshan K. Srinivasan, Scott C. Smith:
Equivalence verification for NULL Convention Logic (NCL) circuits. 195-201
Non-volatile Memory
- Congming Gao, Liang Shi, Kaijie Wu, Chun Jason Xue
Exploit asymmetric error rates of cell states to improve the performance of flash memory storage systems. 202-207 - Fei Xia, Dejun Jiang, Jin Xiong, Ninghui Sun:
Write-aware random page initialization for non-volatile memory systems. 208-215 - Youyou Lu, Jiwu Shu, Long Sun, Onur Mutlu:
Loose-Ordering Consistency for persistent memory. 216-223 - Seungjae Baek, Daeyeon Son, Dongwoo Kang, Jongmoo Choi, Sangyeun Cho:
Design space exploration of an NVM-based memory hierarchy. 224-229
Physical Design
- Can Sitik, Scott Lerner, Baris Taskin:
Timing characterization of clock buffers for clock tree synthesis. 230-236 - Chia-Chi Huang, Chang-Tzu Lin, Wei-Syun Liao, Chieh-Jui Lee, Hung-Ming Chen, Chia-Hsin Lee, Ding-Ming Kwai:
Improving power delivery network design by practical methodologies. 237-242 - Jiun-Yi Chiang, Jun-Hua Kuo, Ting-Shuo Hsu, Jing-Jia Liou:
Chip clustering with mutual information on multiple clock tests and its application to yield tuning. 243-248 - Chi-Yuan Liu, Yao-Wen Chang
Simultaneous EUV flare- and CMP-aware placement. 249-255 - Fulya Kaplan, Charlie De Vivero, Samuel Howes, Manish Arora, Houman Homayoun, Wayne P. Burleson, Dean M. Tullsen
Modeling and analysis of Phase Change Materials for efficient thermal management. 256-263
Dynamic Optimization Techniques for Power, Performance
- Chen Liu, Chengmo Yang:
Improving multilevel PCM reliability through age-aware reading and writing strategies. 264-269 - Xin Tong, Andreas Moshovos:
BarTLB: Barren page resistant TLB for managed runtime languages. 270-277 - Jiyang Yu, Peng Liu:
A Thread-Aware Adaptive Data Prefetcher. 278-285 - Tao Zhang
Dynamic front-end sharing in graphics processing units. 286-291 - Walid J. Ghandour, Nadine J. Ghandour:
Leveraging dynamic slicing to enhance indirect branch prediction. 292-299
Special Session B: Variability, Modeling and Margin at 10nm
- Robert C. Aitken, David Pietromonaco, Brian Cline:
DFM is dead - Long live DFM. 300-307 - Rani S. Ghaida, Yasmine Badr, Puneet Gupta
Pattern-restricted design at 10nm and beyond. 308-310 - Tuck-Boon Chan, Sorin Dobre, Andrew B. Kahng:
Improved signoff methodology with tightened BEOL corners. 311-316
Hardware-software Interaction
- Beayna Grigorian, Glenn Reinman:
Accelerating divergent applications on SIMD architectures using neural networks. 317-323 - Satoshi Imamura
Power-capped DVFS and thread allocation with ANN models on modern NUMA systems. 324-331 - Ying Zhang, Li Zhao, Ramesh Illikkal, Ravi R. Iyer, Andrew Herdrich, Lu Peng:
QoS management on heterogeneous architecture for parallel applications. 332-339 - Yogesh Murarka, Pankaj Shailendra Gode, Sirish Kumar Pasupuleti, Soma Kohli:
Software pipelining of dataflow programs with dynamic constructs on multi-core processor. 340-347 - Daming Zhang, Shuangchen Li, Ang Li, Yongpan Liu, Xiaobo Sharon Hu
Intra-task scheduling for storage-less and converter-less solar-powered nonvolatile sensor nodes. 348-354
Emerging Circuits and Computing Concepts
- Behnam Sedighi, Joseph J. Nahas, Michael T. Niemier, Xiaobo Sharon Hu
Boolean circuit design using emerging tunneling devices. 355-360 - Hideyuki Ichihara, Shota Ishii, Daiki Sunamori, Tsuyoshi Iwagaki, Tomoo Inoue:
Compact and accurate stochastic circuits with shared random number sources. 361-366 - Te-Hsuan Chen, John P. Hayes:
Analyzing and controlling accuracy in stochastic circuits. 367-373 - Alireza Shafaei, Yanzhi Wang, Massoud Pedram:
Low write-energy STT-MRAMs using FinFET-based access transistors. 374-379 - Qing Xie, Yanzhi Wang, Shuang Chen, Massoud Pedram:
Variation-aware joint optimization of the supply voltage and sleep transistor size for the 7nm FinFET technology. 380-385
Architecture and Design
- Chris Fallin, Chris Wilkerson, Onur Mutlu:
The heterogeneous block architecture. 386-393 - Amr Elshennawy, Sunil P. Khatri:
An asynchronous Network-on-Chip router with low standby power. 394-399 - Xiang Pan, Radu Teodorescu:
NVSleep: Using non-volatile memory to enable fast sleep/wakeup of idle cores. 400-407 - Elliott Forbes, Niket Kumar Choudhary, Brandon H. Dwiel, Eric Rotenberg:
Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores. 408-415 - Ryota Shioya, Hideki Ando:
Energy efficiency improvement of renamed trace cache through the reduction of dependent path length. 416-423
Architectural Framework
- Costas Iordanou, Vassos Soteriou
Hermes: Architecting a top-performing fault-tolerant routing algorithm for Networks-on-Chips. 424-431 - Yaman Umuroglu, Magnus Jahre
An energy efficient column-major backend for FPGA SpMV accelerators. 432-439 - Paula Aguilera, Katherine Morrow, Nam Sung Kim:
Fair share: Allocation of GPU resources for both performance and fairness. 440-447 - Pietro Mercati
Dynamic variability management in mobile multicore processors under lifetime constraints. 448-455
System-Level Design and Power Management
- Guanwen Zhong, Vanchinathan Venkataramani, Yun Liang, Tulika Mitra
Design space exploration of multiple loops on FPGAs using high level synthesis. 456-463 - Vinay B. Y. Kumar
Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping. 464-469 - Yuchun Ma, Jinglan Liu, Chao Zhang, Wayne Luk:
HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs. 470-476 - Xue Lin, Yanzhi Wang, Naehyuck Chang, Massoud Pedram:
Power supply and consumption co-optimization of portable embedded systems with hybrid power supply. 477-482 - Massimo Petricca, Donghwa Shin, Alberto Bocca, Alberto Macii
Automated generation of battery aging models from datasheets. 483-488
Posters
- Stelios N. Neophytou
Optimal variable ordering in ZBDD-based path representations for directed acyclic graphs. 489-492 - Raghavan Kumar, Wayne P. Burleson:
Hybrid modeling attacks on current-based PUFs. 493-496 - Ozan Tuncer, Kalyan Vaidyanathan, Kenny C. Gross, Ayse K. Coskun
CoolBudget: Data center power budgeting with workload and cooling asymmetry awareness. 497-500 - Siddharth Advani
Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems. 501-504 - Chris S. Lee, Kevin M. Irick, Jack Sampson, Chuanjun Zhang, Vijaykrishnan Narayanan:
Exploiting natural redundancy in visual information. 505-508 - Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Awet Yemane Weldezion, Pasi Liljeberg, Juha Plosila
Dark silicon aware power management for manycore systems under dynamic workloads. 509-512 - N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones:
Cache design for mixed criticality real-time systems. 513-516 - Giordano Salvador, Siddharth Nilakantan
Static thread mapping for NoCs via binary instrumentation traces. 517-520 - Yao Li
ScalaHDL: Express and test hardware designs in a Scala DSL. 521-524 - Nishit Ashok Kapadia, Sudeep Pasricha:
PRATHAM: A power delivery-aware and thermal-aware mapping framework for parallel embedded applications on 3D MPSoCs. 525-528
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-13 18:59 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: