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15th HPCA 2009: Raleigh, North Carolina, USA
- 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA. IEEE Computer Society 2009, ISBN 978-1-4244-2932-5
Keynote Session I
- Prith Banerjee:
An intelligent IT infrastructure for the future. 3-4
Best Paper Nominees
- Eiman Ebrahimi, Onur Mutlu, Yale N. Patt:
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. 7-17 - Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. Holloway, Gu-Yeon Wei, Michael D. Smith, David M. Brooks:
Voltage emergency prediction: Using signatures to reduce operating margins. 18-29 - Yi Xu, Yu Du, Bo Zhao, Xiuyi Zhou, Youtao Zhang, Jun Yang:
A low-radix and low-diameter 3D interconnection network design. 30-42
Multicore Cache Architectures
- Moinuddin K. Qureshi:
Adaptive Spill-Receive for robust high-performance caching in CMPs. 45-54 - Sangmin Seo, Jaejin Lee, Zehra Sura:
Design and implementation of software-managed caches for multicores with local memory. 55-66 - Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha:
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects. 67-78 - Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos:
Practical off-chip meta-data for temporal memory streaming. 79-90
Reliability
- Xin Fu, Tao Li, José A. B. Fortes:
Soft error vulnerability aware process variation mitigation. 93-104 - Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve:
Accurate microarchitecture-level fault modeling for studying hardware faults. 105-116 - Vilas Sridharan, David R. Kaeli:
Eliminating microarchitectural dependency from Architectural Vulnerability. 117-128 - Lide Duan, Bin Li, Lu Peng:
Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics. 129-140
Panel
- Mark D. Hill:
Opportunities beyond single-core microprocessors. 143-144
Keynote II
- Yale N. Patt:
Multi-core demands multi-interfaces. 147-148
On-Chip Networks-I
- George Michelogiannakis
, James D. Balfour, William J. Dally:
Elastic-buffer flow control for on-chip networks. 151-162 - Boris Grot
Express Cube Topologies for on-Chip Interconnects. 163-174 - Reetuparna Das
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. 175-186
Processor Microarchitecture-I
- Hashem Hashemi Najaf-abadi, Eric Rotenberg:
Architectural Contesting. 189-200 - Mark Stephenson, Lixin Zhang, Ram Rangan:
Lightweight predication support for out of order processors. 201-212 - Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles:
Blueshift: Designing processors for timing speculation from the ground up. 213-224
NUCA and 3D Stacked Memory Hierarchies
- Mainak Chaudhuri:
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches. 227-238 - Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen:
A novel architecture of the 3D stacked MRAM L2 cache for CMPs. 239-249 - Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John B. Carter:
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches. 250-261 - Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer, Srihari Makineni, Donald Newell:
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. 262-274
Power/Performance-Efficient Architectures and Accelerators
- Sami Yehia, Sylvain Girbal
Reconciling specialization and flexibility through compound circuits. 277-288 - Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit Riaz Sheikh, Shrirang M. Yardi:
CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. 289-300 - Sebastian Herbert, Diana Marculescu
Variation-aware dynamic voltage/frequency scaling. 301-312 - Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke:
Bridging the computation gap between programmable processors and hardwired accelerators. 313-322
Industrial Perspectives Panel
- Parthasarathy Ranganathan:
Industrial perspectives panel. 325-326
Performance Modeling and Analysis
- Xi E. Chen, Tor M. Aamodt:
A first-order fine-grained multithreaded throughput model. 329-340 - Amit Kumar, Ram Huggahalli, Srihari Makineni:
Characterization of Direct Cache Access on multi-core systems and 10GbE. 341-352
On-Chip Networks-II
- Pablo Abad Fidalgo
MRR: Enabling fully adaptive multicast routing for CMP interconnection networks. 355-366 - Hiroki Matsutani, Michihiro Koibuchi
Prediction router: Yet another low latency on-chip router architecture. 367-378
Security, Verification, and Validation
- Yunji Chen
Fast complete memory consistency verification. 381-392 - Jingfei Kong, Onur Aciiçmez, Jean-Pierre Seifert, Huiyang Zhou
Hardware-software integrated approaches to defend against software cache-based side channel attacks. 393-404 - Andrew DeOrio, Ilya Wagner, Valeria Bertacco:
Dacota: Post-silicon validation of the memory subsystem in multi-core designs. 405-416
Processor Microarchitecture-II
- Samantika Subramaniam, Anne Bracy, Hong Wang, Gabriel H. Loh:
Criticality-based optimizations for efficient load processing. 419-430 - Andrew D. Hilton, Santosh Nagarakatte
iCFP: Tolerating all-level cache misses in in-order processors. 431-442 - Ibrahim Hur, Calvin Lin:
Feedback mechanisms for improving probabilistic memory prefetching. 443-454
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