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13th HPCA 2007: Phoenix, Arizona, USA
- 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA. IEEE Computer Society 2007, ISBN 1-4244-0804-0
- William J. Dally:
Interconnect-Centric Computing. 1 - Haakon Dybdahl, Per Stenström:
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors. 2-12 - Colby Ranger, Ramanan Raghuraman, Arun Penmetsa, Gary R. Bradski, Christos Kozyrakis:
Evaluating MapReduce for Multi-core and Multiprocessor Systems. 13-24 - Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlke:
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications. 25-36 - Murali Annavaram
, Ed Grochowski, Paul Reed:
Implications of Device Timing Variability on Full Chip Timing. 37-45 - Yasunao Katayama, Atsuya Okazaki
Optical Interconnect Opportunities for Future Server Memory Systems. 46-50 - Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt:
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. 63-74 - Eduardo Quiñones
Improving Branch Prediction and Predicated Execution in Out-of-Order Processors. 75-84 - Weifeng Zhang, Dean M. Tullsen
Accelerating and Adapting Precomputation Threads for Effcient Prefetching. 85-95 - Steve Pawlowski:
Petascale Computing Research Challenges - A Manycore Perspective. 96 - Hassan Chafi, Jared Casper, Brian D. Carlstrom, Austen McDonald, Chi Cao Minh, Woongki Baek, Christos Kozyrakis, Kunle Olukotun:
A Scalable, Non-blocking Approach to Transactional Memory. 97-108 - Brinda Ganesh, Aamer Jaleel, David Wang, Bruce L. Jacob:
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling. 109-120 - Pin Zhou, Radu Teodorescu, Yuanyuan Zhou:
HARD: Hardware-Assisted Lockset-based Race Detection. 121-132 - Luis Ceze, Pablo Montesinos, Christoph von Praun, Josep Torrellas:
Colorama: Architectural Support for Data-Centric Synchronization. 133-144 - Albert Meixner, Daniel J. Sorin:
Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures. 145-156 - Ricardo Fernández Pascual
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures. 157-168 - Paul Racunas, Kypros Constantinides, Srilatha Manne, Shubhendu S. Mukherjee:
Perturbation-based Fault Screening. 169-180 - Xuanhua Li, Donald Yeung:
Application-Level Correctness and its Impact on Fault Tolerance. 181-192 - Kiran Puttaswamy, Gabriel H. Loh:
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. 193-204 - Jeonghwan Choi, Youngjae Kim, Anand Sivasubramaniam, Jelena Srebric, Qian Wang, Joonwon Lee:
Modeling and Managing Thermal Profiles of Rack-mounted Servers with ThermoStat. 205-215 - Nathan Clark, Amir Hormati, Sami Yehia, Scott A. Mahlke, Krisztián Flautner:
Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping. 216-227 - Alaa R. Alameldeen, David A. Wood:
Interactions Between Compression and Prefetching in Chip Multiprocessors. 228-239 - Stijn Eyerman, Lieven Eeckhout:
A Memory-Level Parallelism Aware Fetch Policy for SMT Processors. 240-249 - Moinuddin K. Qureshi, M. Aater Suleman, Yale N. Patt:
Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines. 250-259 - Luke Yen, Jayaram Bobba, Michael R. Marty, Kevin E. Moore, Haris Volos, Mark D. Hill, Michael M. Swift, David A. Wood:
LogTM-SE: Decoupling Hardware Transactional Memory from Caches. 261-272 - Guru Venkataramani, Brandyn Roemer, Yan Solihin, Milos Prvulovic:
MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging. 273-284 - Jun Shao, Brian T. Davis:
A Burst Scheduling Access Reordering Mechanism. 285-294 - Mayank Agarwal, Kshitiz Malik, Kevin M. Woley, Sam S. Stone, Matthew I. Frank:
Exploiting Postdominance for Speculative Parallelization. 295-305 - Jeffrey Shafer, David Carr, Aravind Menon, Scott Rixner, Alan L. Cox, Willy Zwaenepoel, Paul Willmann:
Concurrent Direct Network Access for Virtual Machine Monitors. 306-317 - Yuho Jin, Eun Jung Kim, Ki Hwan Yum:
A Domain-Specific On-Chip Network Design for Large Scale Cache Systems. 318-327 - Liqun Cheng, John B. Carter, Donglai Dai:
An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing. 328-339 - Benjamin C. Lee, David M. Brooks:
Illustrative Design Space Studies with Microarchitectural Regression Models. 340-351
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