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HLDVT 2011: Napa Valley, CA, USA
- Zeljko Zilic, Sandeep K. Shukla:
2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1744-4
Equivalence Checking
- Wei Hu, Huy Nguyen, Michael S. Hsiao:
Sufficiency-based filtering of invariants for Sequential Equivalence Checking. 1-8 - Bijan Alizadeh, Masahiro Fujita:
Modular equivalence verification of polynomial datapaths with multiple word-length operands. 9-16 - Hans Eveking, Tobias Dornes, Martin Schweikert:
Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs. 17-24
Formal Models and Verification
- Mike Gemünde, Jens Brandt
, Klaus Schneider
Causality analysis of synchronous programs with refined clocks. 25-32 - Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli
UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design. 33-40 - Somnath Banerjee, Tushar Gupta, Saurabh Jain:
A scalable hybrid verification system based on HDL slicing. 41-48
Coverage & Tests
- Peter Lisherness, Kwang-Ting (Tim) Cheng
Coverage discounting: A generalized approach for testbench qualification. 49-56 - Charalambos Ioannides, Geoff Barrett
Introducing XCS to Coverage Directed test Generation. 57-64 - Tao Xie, Wolfgang Müller, Florian Letombe:
IP-XACT based system level mutation testing. 65-71 - Hansu Cho, Samar Abdi:
Automatic generation of transducer models for multicore system design. 72-79
Interactive Session
- Giuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli
Interactive presentation abstract: Assertion-based verification in embedded-software design. 80 - Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli
Interactive presentation abstract: Reusing of properties after discretization of hybrid automata. 81 - Alexander W. Rath, Volkan Esen, Wolfgang Ecker:
Analog transaction level modeling. 82 - Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik:
Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams. 83
Post Silicon Validation & Reliable Design
- Charlie Shucheng Zhu, Georg Weissenbacher
SAT-based techniques for determining backbones for post-silicon fault localisation. 84-91 - Mehdi Karimibiuki, Kyle Balston, Alan J. Hu, André Ivanov:
Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC. 92-97 - Andrea Pellegrini, Valeria Bertacco:
Cardio: Adaptive CMPs for reliability through dynamic introspective operation. 98-105
Invited Papers
- Gunar Schirner:
Modeling, synthesis, and validation of heterogeneous biomedical embedded systems. 106-109 - Matin Hashemi
Towards scalable utilization of embedded manycores in throughput-sensitive applications. 110-115 - Frederic Risacher, Kenneth J. Schultz:
Software agnostic approaches to explore pre-silicon system performance. 116-120
Validation Techniques
- Amir Masoud Gharehbaghi
Formal verification guided automatic design error diagnosis and correction of complex processors. 121-127 - Min Li, Kelson Gent, Michael S. Hsiao:
Utilizing GPGPUs for design validation with a modified Ant Colony Optimization. 128-135 - Jinpeng Lv, Priyank Kalla, Florian Enescu:
Verification of composite Galois field multipliers over GF ((2m)n) using computer algebra techniques. 136-143
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