default search action
ACM Great Lakes Symposium on VLSI 2020: Virtual Event, China
- Tinoosh Mohsenin, Weisheng Zhao, Yiran Chen, Onur Mutlu:
GLSVLSI '20: Great Lakes Symposium on VLSI 2020, Virtual Event, China, September 7-9, 2020. ACM 2020, ISBN 978-1-4503-7944-1
Keynote I
- Hoi-Jun Yoo:
Deep Learning Processors for On-Device Intelligence. 1-8
Session 1A: Machine Learning and Neuromorphic Accelerator Designs
- Shiming Li, Shasha Guo, Limeng Zhang, Ziyang Kang, Shiying Wang, Wei Shi, Lei Wang, Weixia Xu:
SNEAP: A Fast and Efficient Toolchain for Mapping Large-Scale Spiking Neural Network onto NoC-based Neuromorphic Platform. 9-14 - Jiacheng Ni, Xiaochen Guo, Yuanqing Cheng:
SIP: Boosting Up Graph Computing by Separating the Irregular Property Data. 15-20 - Hongjie Xu, Jun Shiomi, Hidetoshi Onodera:
On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation. 21-26 - Dharanidhar Dang, Aurosmita Khansama, Rabi N. Mahapatra, Debashis Sahoo:
BPhoton-CNN: An Ultrafast Photonic Backpropagation Accelerator for Deep Learning. 27-32
Session 1B: Emerging Memory-Enabled Computing for Future Electronics
- Grace Li Zhang
, Bing Li, Ying Zhu, Shuhang Zhang, Tianchen Wang, Yiyu Shi, Tsung-Yi Ho
Reliable and Robust RRAM-based Neuromorphic Computing. 33-38 - Dayane Reis
Modeling and Benchmarking Computing-in-Memory for Design Space Exploration. 39-44 - Zheyu Li, Nagadastagiri Challapalle, Akshay Krishna Ramanathan, Vijaykrishnan Narayanan
IMC-Sort: In-Memory Parallel Sorting Architecture using Hybrid Memory Cube. 45-50 - He Zhang, Wang Kang, Youguang Zhang, Weisheng Zhao:
Deep Neural Network accelerator with Spintronic Memory. 51
Session 2A: Hardware Security and Testing
- Rashmi S. Agrawal, Lake Bu, Eliakin Del Rosario, Michel A. Kinsy:
Towards Programmable All-Digital True Random Number Generator. 53-58 - Liang Zheng, Changting Li, Zongbin Liu, Cunqing Ma:
Boosting Entropy Extraction of PDL-based RO PUF by High-order Difference Method. 59-64 - Zhengyi Hou, You Wang, Deming Zhang, Chengzhi Wang, Hao Cai:
A Modeling Attack Resilient Physical Unclonable Function Based on STT-MRAM. 65-70 - Zuodong Zhang, Runsheng Wang, Zhe Zhang, Ru Huang, Chang Meng
Reliability-Enhanced Circuit Design Flow Based on Approximate Logic Synthesis. 71-76
Session 2B: In-Memory Computing for Advanced Machine Learning Applications: An EDA Perspective
- Wei Mao, Zhihua Xiao, Peng Xu, Hongwei Ren, Dingbang Liu, Shirui Zhao
Energy-Efficient Machine Learning Accelerator for Binary Neural Networks. 77-82 - Zhenhua Zhu, Hanbo Sun, Kaizhong Qiu, Lixue Xia, Gokul Krishnan, Guohao Dai, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems. 83-88 - Sathwika Bavikadi
A Review of In-Memory Computing Architectures for Machine Learning Applications. 89-94
Session 3A: 3D Flash Memory and FPGA Designs
- Jinhua Cui, Weiguang Liu, Jianhang Huang, Laurence T. Yang:
Exploiting Disturbance-Aware Read Redirection for Performance Improvement in 3D Flash Memory. 95-100 - Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, Rolf Drechsler
Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes. 101-106 - Zhen Zhuang, Genggeng Liu, Xing Huang, Xiaotao Jia, Wen-Hao Liu, Wenzhong Guo:
MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique. 107-112 - Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai:
A Tile-based Interconnect Model for FPGA Architecture Exploration. 113-118
Session 3B: Efficient and Secure Deep Learning and Reinforcement Learning in Embedded Systems
- Yifan Gong, Zheng Zhan, Zhengang Li, Wei Niu
A Privacy-Preserving-Oriented DNN Pruning and Mobile Acceleration Framework. 119-124 - Adnan Siraj Rakin, Zhezhi He, Li Yang, Yanzhi Wang, Liqiang Wang, Deliang Fan:
Robust Sparse Regularization: Defending Adversarial Attacks Via Regularized Sparse Network. 125-130 - Aidin Shiri, Arnab Neelim Mazumder, Bharat Prakash, Nitheesh Kumar Manjunath
Energy-Efficient Hardware for Language Guided Reinforcement Learning. 131-136
Keynote II
- Fadi J. Kurdahi:
Towards Self-Aware Systems-on-Chip Through Intelligent Cross-Layer Coordination. 137
Session 4A: Emerging Computing Circuits, Architectures, and Paradigms
- Rajat Bhattacharjya
An Approximate Carry Estimating Simultaneous Adder with Rectification. 139-144 - Rongliang Fu
Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits. 145-150 - Zahra Ebrahimi
SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy. 151-156 - Sina Asadi, M. Hassan Najafi:
Accelerating Deterministic Stochastic Computing with Context-Aware Bit-stream Generator. 157-162
Session 4B: Advances in Microarchitecture Security: from Detection of Threats to Mitigation
- Claudio Canella, Khaled N. Khasawneh, Daniel Gruss:
The Evolution of Transient-Execution Attacks. 163-168 - Claudio Canella, Sai Manoj Pudukotai Dinakarrao
Evolution of Defenses against Transient-Execution Attacks. 169-174 - Hossein Sayadi, Yifeng Gao, Hosein Mohammadi Makrani, Tinoosh Mohsenin, Avesta Sasan, Setareh Rafatirad, Jessica Lin, Houman Homayoun:
StealthMiner: Specialized Time Series Machine Learning for Run-Time Stealthy Malware Detection based on Microarchitectural Features. 175-180 - Han Wang, Hossein Sayadi, Avesta Sasan, Setareh Rafatirad, Tinoosh Mohsenin, Houman Homayoun:
Comprehensive Evaluation of Machine Learning Countermeasures for Detecting Microarchitectural Side-Channel Attacks. 181-186
Session 5A: Neural Network Acceleration and Approximate Computing
- Wonjae Lee, Yonghwi Kwon, Youngsoo Shin:
Fast ECO Leakage Optimization Using Graph Convolutional Network. 187-192 - Bo Liu, Yuhao Sun, Hao Cai, Zeyu Shen, Yu Gong, Lepeng Huang, Zhen Wang:
An Ultra-low Power Keyword-Spotting Accelerator Using Circuit-Architecture-System Co-design and Self-adaptive Approximate Computing Based BWN. 193-198 - Sheng Xu, Xiaoming Chen, Xuehai Qian, Yinhe Han:
TUPIM: A Transparent and Universal Processing-in-Memory Architecture for Unmodified Binaries. 199-204 - Zhixi Yang, Honglan Jiang, Xianbin Li, Jun Yang:
Power-Efficient Approximate Multiplier Using Adaptive Error Compensation. 205-210
Session 5B: Protecting the Hardware in the Manufacturing Supply Chain: A Special Session on Hardware Security
- Tamzidul Hoque, Patanjali SLPSK, Swarup Bhunia
Trust Issues in COTS: The Challenges and Emerging Solution. 211-216 - Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic. 217-222 - Zhichao Xu, Aijiao Cui, Gang Qu:
A New Aging Sensor for the Detection of Recycled ICs. 223-228 - Md Tanvir Arafin
Security Challenges of Processing-In-Memory Systems. 229-234
Session 6A: Network-on-Chip Designs and On-Chip Communication
- Febin Sunny, Asif Mirza, Ishan G. Thakkar, Sudeep Pasricha, Mahdi Nikdast:
LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip. 235-240 - Yuan He
Energy-Efficient On-Chip Networks through Profiled Hybrid Switching. 241-246 - Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar:
Redesigning Photonic Interconnects with Silicon-on-Sapphire Device Platform for Ultra-Low-Energy On-Chip Communication. 247-252 - Tian Xia, Pengchen Zong, Haoran Zhao, Jianming Tong, Wenzhe Zhao, Nanning Zheng, Pengju Ren:
COCOA: Content-Oriented Configurable Architecture Based on Highly-Adaptive Data Transmission Networks. 253-258
Session 6B: When Energy Efficiency and Multi-level Interaction Work Together
- Zhe Huang, Yue Zhang, Kun Zhang, Zhizhong Zhang, Jinkai Wang, Youguang Zhang, Weisheng Zhao:
An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device. 259-264 - Yufei Ma, Yuan Du, Li Du, Jun Lin, Zhongfeng Wang:
In-Memory Computing: The Next-Generation AI Computing Paradigm. 265-270 - Bo Liu, Yan Li, Lepeng Huang, Hao Cai, Wentao Zhu, Shisheng Guo, Yu Gong, Zhen Wang:
A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing. 271-275 - Shaahin Angizi, Wei Zhang
Exploring DNA Alignment-in-Memory Leveraging Emerging SOT-MRAM. 277-282
Keynote III
- Cong Hao, Yao Chen
Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices. 283-290
Session 7A: Machine-learning based Design Automation
- Zhuoran Song, Yilong Zhao
ESNreram: An Energy-Efficient Sparse Neural Network Based on Resistive Random-Access Memory. 291-296 - Niklas Bruns, Daniel Große, Rolf Drechsler
Early Verification of ISA Extension Specifications using Deep Reinforcement Learning. 297-302 - Mengke Ge, Qi Xu, Huajie Ruan, Xiaobing Ni, Song Chen, Yi Kang:
Synthesizing A Generalized Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems. 303-308 - Wei Bao, Peng Cao, Hao Cai, Aiguo Bu:
A Learning-Based Timing Prediction Framework for Wide Supply Voltage Design. 309-314
Session 7B: Security in/for Approximate Computing
- Yuqin Dou
Security Analysis of Hardware Trojans on Approximate Circuits. 315-320 - Francesco Regazzoni
Side Channel Attacks vs Approximate Computing. 321-326 - Pruthvy Yellu, Landon Buell, Dongpeng Xu
Blurring Boundaries: A New Way to Secure Approximate Computing Systems. 327-332 - Ye Wang, Jian Dong, Qian Xu, Zhaojun Lu, Gang Qu:
Is It Approximate Computing or Malicious Computing? 333-338
Session 8: Emering Deep Neural Network Computing and In-Memory Computing Systems
- Baogang Zhang
Redundant Neurons and Shared Redundant Synapses for Robust Memristor-based DNNs with Reduced Overhead. 339-344 - Zihan Zhang, Taozhong Li, Ning Guan, Qin Wang, Guanghui He, Weiguang Sheng, Zhigang Mao, Naifeng Jing:
Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration. 345-350 - Yining Bai, Yue Zhang, Jinkai Wang, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Kun Zhang, Weisheng Zhao:
A Novel In-memory Computing Scheme Based on Toggle Spin Torque MRAM. 351-356 - Ziqian Wan, Guohao Dai, Yun Joon Soh, Jishen Zhao, Yu Wang:
An Order Sampling Processing-in-Memory Architecture for Approximate Graph Pattern Mining. 357-362
Panel I: Cross-Layer Design of Cyber-Physical Systems: from Circuit to Cloud
- Dongning Ma, Xunzhao Yin, Michael T. Niemier, Xiaobo Sharon Hu
AxR-NN: Approximate Computation Reuse for Energy-Efficient Convolutional Neural Networks. 363-368 - Keni Qiu, Mengying Zhao, Zhenge Jia
Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems. 369-374 - Meng Dong, Zhiliang Qiu, Weitao Pan, Hongbin Zhang, Chenglei Kong, Hui Jin, Jianlei Yang:
Dual-Plane Switch Architecture for Time-Triggered Ethernet. 375-379 - Jingxian Cheng, Saiyu Qi, Wenqing Wang, Yuchen Yang, Yong Qi:
Fast Consistency Auditing for Massive Industrial Data in Untrusted Cloud Services. 381-386
Poster Session I
- Wei Lu, Yuhang Zhang, Qing Zhang, Xinjie Zhang, Yongfu Li:
Litho-NeuralODE: Improving Hotspot Detection Accuracy with Advanced Data Augmentation and Neural Ordinary Differential Equations. 387-392 - Zhaopo Liao, Sheqin Dong:
A Constraint-Driven Compact Model with Partition Strategy for Ordered Escape Routing. 393-398 - Wei Wang, Vasilis F. Pavlidis, Yuanqing Cheng:
Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength. 399-404 - Lorenzo Servadei, Edoardo Mosca, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker, Robert Wille:
Cost Estimation for Configurable Model-Driven SoC Designs Using Machine Learning. 405-410 - Yina Lv, Liang Shi, Chun Joseph Xue, Qingfeng Zhuge, Edwin H.-M. Sha:
Latency Variation Aware Read Performance Optimization on 3D High Density NAND Flash Memory. 411-414 - Guorong He, Chen Dong, Xing Huang, Wenzhong Guo, Ximeng Liu, Tsung-Yi Ho
HTcatcher: Finite State Machine and Feature Verifcation for Large-scale Neuromorphic Computing Systems. 415-420 - Muhammad Awais
A Hybrid Synthesis Methodology for Approximate Circuits. 421-426 - Segi Lee, Sugil Lee, Jongeun Lee, Jong-Moon Choi, Do-Wan Kwon, Seung-Kwang Hong, Kee-Won Kwon:
Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor. 427-432 - Xingbin Jiang, Michele Lora, Sudipta Chattopadhyay:
Efficient and Trusted Detection of Rootkit in IoT Devices via Offline Profiling and Online Monitoring. 433-438 - Lingxuan Zhang, Linsen Li, Futai Zou, Jiachao Niu:
Quantitatively Assessing the Cyber-to-Physical Risk of Industrial Cyber-Physical Systems. 439-444
Poster Session II
- Liqi Ping, Jingweijia Tan, Kaige Yan:
SERN: Modeling and Analyzing the Soft Error Reliability of Convolutional Neural Networks. 445-450 - Xiaojing Zha, Yinshui Xia:
Defect-Tolerant Mapping of CMOL Circuits with Delay Optimization. 451-456 - Dawen Xu, Cheng Chu, Cheng Liu, Ying Wang, Xianzhong Zhou
Multi-task Scheduling for PIM-based Heterogeneous Computing System. 457-462 - Seungseok Nam, Emil Matús, Gerhard P. Fettweis:
An ASIP Approach to Path Allocation in TDM NoCs using Adaptive Search Region. 463-468 - Zhitao Yang, Yucong Huang, Jianghan Zhu, Terry Tao Ye
Analog Circuit Implementation of LIF and STDP Models for Spiking Neural Networks. 469-474 - Zhe Chen, Yuelong Zhao:
DA-GC: A Dynamic Adjustment Garbage Collection Method Considering Wear-leveling for SSD. 475-480 - Yuxin Yang
Accelerating RRT Motion Planning Using TCAM. 481-486 - Chirag Joshi, Palash Das, Ashwini A. Kulkarni
Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors. 487-492 - Yucong Huang, Zhitao Yang, Jianghan Zhu, Terry Tao Ye
Analog Circuit Implementation of Neurons with Multiply-Accumulate and ReLU Functions. 493-498
Keynote IV
- Shirin Haji Amin Shirazi, Hoda Naghibijouybari
Securing Machine Learning Architectures and Systems. 499-506
Session 9: 3D Circuits and Power Circuits
- Philipp Schlicker, Oliver Bringmann:
Gate-Level Models for Fast Cross-Level Power Density Estimation. 507-512 - Halima Najibi, Alexandre Levisse, Marina Zapater, Mohamed M. Sabry Aly, David Atienza:
Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology. 513-518 - Minmin Jiang, Ioannis A. Papistas, Vasilis F. Pavlidis:
Cost Modeling and Analysis of TSV and Contactless 3D-ICs. 519-524 - Siyao Zhu, Jian Zhao, Yongfu Li, Mingyi Chen:
A 53%-PTE and 4-Mbps Power and Data Telemetry Circuit based on Adaptive Duty-cycling BPSK Modulated Class-E Amplifier. 525-530
Panel II: Security and Privacy Issues in AI and Their Impacts on Hardware Security
- Jiliang Zhang, Chen Li, Jing Ye, Gang Qu:
Privacy Threats and Protection in Machine Learning. 531-536 - Qingli Guo, Jing Ye, Jiliang Zhang, Yu Hu, Xiaowei Li
Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs. 537-542 - Bo Luo, Min Li, Yu Li, Qiang Xu
On Configurable Defense against Adversarial Example Attacks. 543-548 - Heng Liu, Linzhi Jiang, Jian Xu, Dexin Wu, Liqun Chen:
Adversarial Perturbation with ResNet. 549-554
Session 10: Microelectronic Systems Education Workshop
- Noah Boorstin, Veronica Cortes, Kaveh Pezeshki
A Simplified Arm Processor for VLSI Education. 555-559 - Kaveh Pezeshki
A Board and Projects for an FPGA/Microcontroller-Based Embedded Systems Lab. 561-565 - Jianlei Yang, Xiaopeng Gao, Weisheng Zhao:
Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures. 567-572 - Han Yu, Chao Guo, Bin Chen, Changxin Du, Xiao Yong, Senhua Fan:
A New Silicon-aware Big Data SoC Timing Analysis Solution: A Case Study of Empyrean University Program. 573-578
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-13 18:59 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: