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FPT 2011: New Delhi, India
- Russell Tessier:
2011 International Conference on Field-Programmable Technology, FPT 2011, New Delhi, India, December 12-14, 2011. IEEE 2011, ISBN 978-1-4577-1741-3 - Ioannis Sourdis, Abhijit Nandy, Venkatasubramanian Viswanathan, Anthony Brandon, Dimitris Theodoropoulos, Georgi Gaydadjiev
:
Reconfigurable acceleration and dynamic partial self-reconfiguration in general purpose computing. 1-8 - Brahim Betkaoui, David B. Thomas, Wayne Luk, Natasa Przulj
A framework for FPGA acceleration of large graph problems: Graphlet counting case study. 1-8 - Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura
Cool Mega-Array: A highly energy efficient reconfigurable accelerator. 1-8 - Zhanpeng Jin, Allen C. Cheng:
A self-healing autonomous neural network hardware for trustworthy biomedical systems. 1-8 - Chuan Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio
FPGA implementation of reconfigurable ADPLL network for distributed clock generation. 1-4 - Joseph C. Libby, Ashley Furrow, Paddy O'Brien, Kenneth B. Kent
A framework for verifying functional correctness in Odin II. 1-6 - Bo Duan, Wendi Wang, Xingjian Li
Floating-point mixed-radix FFT core generation for FPGA and comparison with GPU and CPU. 1-6 - Susana Eiroa
An analysis of ring oscillator PUF behavior on FPGAs. 1-4 - Wei Chen, Xiaolin Zhang, Takeshi Yoshimura, Yuichi Nakamura:
A low power technology mapping method for Adaptive Logic Module. 1-5 - Chi Wai Yu, Fred Cox, Wayne Luk, Ray C. C. Cheung
Hydrate: Hybrid Reconfigurable Architecture Expressions. 1-4 - Sunil Malipatlolla, Thomas Feller, Abdulhadi Shoufan
A novel architecture for a secure update of cryptographic engines on trusted platform module. 1-6 - Ratna Krishnamoorthy, Masahiro Fujita, Keshavan Varadarajan, S. K. Nandy:
Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture. 1-5 - Nachiket Kapre
VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration. 1-9 - Kazuhiro Negi, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri:
Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm. 1-8 - Rabia Shahid, Malik Umar Sharif, Marcin Rogawski, Kris Gaj:
Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates. 1-9 - Masayuki Suzuki, Tsutomu Maruyama:
Variable and clause elimination in SAT problems using an FPGA. 1-8 - Adrien Le Masle, Gary Chun Tak Chow, Wayne Luk:
Constant power reconfigurable computing. 1-8 - Senthilkumar Thoravi Rajavel, Ali Akoglu
An analytical energy model to accelerate FPGA logic architecture investigation. 1-8 - Joydip Das, Steven J. E. Wilton:
Accelerated FPGA architecture design: Capabilities and limitations of analytical models. 1-8 - Philip Garcia, Katherine Compton:
A scalable memory interface for multicore reconfigurable computing systems. 1-8 - Kazuei Hironaka, Nobuaki Ozaki, Hideharu Amano:
The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator. 1-4 - Gina C. Adam
3D implication logic: Preliminary results. 1-3 - Kizheppatt Vipin
Enabling high level design of adaptive systems with partial reconfiguration. 1-4 - Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Architecture and tools for programmable QCA. 1-4 - Peter Crosthwaite, John Williams
A unified emulation/simulation environment for reconfigurable system-on-chip development. 1-8 - David Dickin, Lesley Shannon:
Exploring FPGA technology mapping for fracturable LUT minimization. 1-8 - Kong Woei Susanto, Wayne Luk:
Automating formal verification of customized soft-processors. 1-8 - Stefan Wildermann, Felix Reimann, Jürgen Teich, Zoran Salcic
Operational mode exploration for reconfigurable systems with multiple applications. 1-8 - Dimitrios Meidanis, Konstantinos Georgopoulos, Ioannis Papaefstathiou
FPGA power consumption measurements and estimations under different implementation parameters. 1-6 - Qiang Liu, Wayne Luk:
Objective-driven workload allocation in heterogeneous computing systems. 1-4 - Macarena C. Martínez-Rodríguez
Design methodology for FPGA implementation of lattice piecewise-affine functions. 1-4 - Shaojun Wang, Yu Peng, Guangquan Zhao, Xiyuan Peng:
Accelerating on-line training of LS-SVM with run-time reconfiguration. 1-6 - Martin Kumm, Peter Zipf
High speed low complexity FPGA-based FIR filters using pipelined adder graphs. 1-4 - Rohit Kumar, Ann Gordon-Ross:
Formulation-level design space exploration for partially reconfigurable FPGAs. 1-6 - Thomas Marconi, Tulika Mitra
A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs. 1-6 - Chong H. Ang, Craig T. Jin
Spiking neural network-based auto-associative memory using FPGA interconnect delays. 1-4 - Wenqi Bao, Jiang Jiang, Yuzhuo Fu, Qing Sun:
A reconfigurable macro-pipelined systolic accelerator architecture. 1-6 - Aitzan Sari, Mihalis Psarakis:
Scrubbing-based SEU mitigation approach for Systems-on-Programmable-Chips. 1-8 - Saman Kiamehr, Abdulazim Amouri, Mehdi Baradaran Tahoori:
Investigation of NBTI and PBTI induced aging in different LUT implementations. 1-8 - Sunil Malipatlolla, Thomas Feller, Abdulhadi Shoufan, Tolga Arul, Sorin A. Huss:
A novel architecture for a secure update of cryptographic engines on trusted platform module. 1-6 - Sumanta Chaudhuri
Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates. 1-8 - Masayuki Kimura, Kazuei Hironaka, Hideharu Amano:
Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations. 1-8 - Shaon Yousuf, Adam Jacobs, Ann Gordon-Ross:
Partially reconfigurable system-on-chips for adaptive fault tolerance. 1-8 - Lingkan Gong, Oliver Diessel
ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration. 1-8 - André Seffrin, Sorin A. Huss:
Hardware-accelerated execution of Pi-calculus reconfiguration schedules. 1-8 - Aditya Gour, A. Santhana Raj, R. P. Behera, Nagarajan Murali, S. A. V. Satya Murty:
Design & development of soft-core processor based remote terminal units for nuclear reactors. 1-4 - Tejasvi Anand, Yagnesh Waghela, Kuruvilla Varghese:
A scalable network port scan detection system on FPGA. 1-6 - Khadgi Mitesh, Majid H. Koul
An adaptive-method for velocity estimation using time-to-digital converter. 1-4 - Garima Kapur, C. M. Markan:
Design methodology for analog circuit designs using proposed field programmable basic analog building blocks. 1-4 - Antoine Morvan, Steven Derrien, Patrice Quinton:
Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion. 1-10 - Kyle Rupnow
High level synthesis of stereo matching: Productivity, performance, and software constraints. 1-8 - Tassadaq Hussain, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé
Implementation of a Reverse Time Migration kernel using the HCE High Level Synthesis tool. 1-8 - Zhanxiang Zhao, Xi Jin, Xin Zhang:
Pipelined high precision beamforming delay calculator for ultrasound imaging. 1-4 - Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila
Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures. 1-6 - Swamy D. Ponpandi, Akhilesh Tyagi:
Partial reconfiguration logic synthesis by temporal slicing. 1-6 - Abelardo Jara-Berrocal, Ann Gordon-Ross:
Hardware module reuse and runtime assembly for dynamic management of reconfigurable resources. 1-6 - Jérémie Crenne, Pascal Cotret, Guy Gogniat
Efficient key-dependent message authentication in reconfigurable hardware. 1-6 - Chuan Cheng, Christos-Savvas Bouganis
An FPGA-based object detector with dynamic workload balancing. 1-4 - David Castells-Rufas
Sharing FPUs in many-soft-cores. 1-6 - Kentaro Sano:
SW and HW co-design of Connect6 accelerator with scalable streaming cores. 1-4 - Kizheppatt Vipin
A threat-based Connect6 implementation on FPGA. 1-4 - Josef Angermeier, Daniel Ziener
Runtime stress-aware replica placement on reconfigurable devices under safety constraints. 1-6 - Kizheppatt Vipin
Efficient region allocation for adaptive partial reconfiguration. 1-6 - Takahiro Watanabe, Retsu Moriwaki, Yuichiro Yamaji, Yuki Kamikubo, Yuki Torigai, Yuki Nihira, Takashi Yoza, Yumiko Ueno, Yuji Aoyama, Minoru Watanabe:
An FPGA Connect6 Solver with a two-stage pipelined evaluation. 1-4 - Tobias Ziermann, Bernhard Schmidt, Moritz Mühlenthaler, Daniel Ziener
An FPGA implementation of a threat-based strategy for Connect6. 1-4
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