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FPT 2016: Xi'an, China
- Yuchen Song, Shaojun Wang, Brent Nelson, Junbao Li, Yu Peng:
2016 International Conference on Field-Programmable Technology, FPT 2016, Xi'an, China, December 7-9, 2016. IEEE 2016, ISBN 978-1-5090-5602-6
Keynote Lecture
- Jason Helge Anderson:
High-level synthesis - the right side of history. 1 - Andrew Putnam:
The configurable cloud - accelerating hyperscale datacenter services with FPGAs. 2 - Yonghua Lin:
FPGA as service in public Cloud: Why and how. 3
Device
- Kosuke Tatsumura
, Sadegh Yazdanshenas, Vaughn Betz:
High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs. 4-11 - Dennis R. E. Gnad
Analysis of transient voltage fluctuations in FPGAs. 12-19 - He Qi, Oluseyi A. Ayorinde, Benton H. Calhoun:
An energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gating. 20-27
Architecture
- Muhammed Al Kadi, Michael Hübner:
Integer computations with soft GPGPU on FPGAs. 28-35 - Jagath Weerasinghe, Raphael Polig, François Abel, Christoph Hagleitner:
Network-attached FPGAs for data center applications. 36-43 - Tian Xia, Jean-Christophe Prévotet
Hypervisor mechanisms to manage FPGA reconfigurable accelerators. 44-52
Application
- Haomiao Wang, Ming Zhang, Thiagaraj Prabu
FPGA-based acceleration of FDAS module using OpenCL. 53-60 - Zhiqiang Liu, Yong Dou, Jingfei Jiang, Jinwei Xu:
Automatic code generation of convolutional neural networks in FPGA implementation. 61-68 - Yiren Zhao, John Wickerson, George A. Constantinides:
An efficient implementation of online arithmetic. 69-76 - Eriko Nurvitadhi, David Sheffield, Jaewoong Sim, Asit K. Mishra, Ganesh Venkatesh, Debbie Marr:
Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC. 77-84 - Sean Fox, Stephen Tridgell, Craig T. Jin
Random projections for scaling machine learning on FPGAs. 85-92 - Denis Matousek, Jan Korenek, Viktor Pus:
High-speed regular expression matching with pipelined automata. 93-100
Reliability
- Zhuoran Zhao, Dimitris Agiakatsikas
Fine-grained module-based error recovery in FPGA-based TMR systems. 101-108 - Jose P. Pinilla, Steven J. E. Wilton:
Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs. 109-116 - Lingkan Gong, Tong Wu
A Programmable Configuration Controller for fault-tolerant applications. 117-124
High Level Synthesis (HLS)
- Juan Escobedo, Mingjie Lin:
Tessellation-based multi-block memory mapping scheme for high-level synthesis with FPGA. 125-132 - Björn Liebig, Andreas Koch:
High-level synthesis of resource-shared microarchitectures from irregular complex C-code. 133-140 - Quentin Gautier, Alric Althoff, Pingfan Meng, Ryan Kastner
Spector: An OpenCL FPGA benchmark suite. 141-148
Network on Chip (NoC)
- Kumar H. B. Chethan, Shubham Agarwal, Nachiket Kapre:
Deflection routing for multi-level FPGA overlay NoCs. 149-156 - Tianqi Liu, Naveen Kumar Dumpala, Russell Tessier:
Hybrid hard NoCs for efficient FPGA communication. 157-164
Poster
- David Sidler, Ken Eguro:
Debugging framework for FPGA-based soft processors. 165-168 - Nguyen T. H. Nguyen, Dimitris Agiakatsikas
Dynamic scheduling of voter checks in FPGA-based TMR systems. 169-172 - Wei Ting Loke, Chin Yang Koay:
Energy-aware scheduling for task adaptive FPGAs. 173-176 - Lana Josipovic
Enriching C-based High-Level Synthesis with parallel pattern templates. 177-180 - Grace Zgheib, Paolo Ienne:
Automatic wire modeling to explore novel FPGA architectures. 181-184 - Deshya Wijesundera, Alok Prakash, Thambipillai Srikanthan:
Rapid design space exploration for soft core processor customization and selection. 185-188 - Georgios Tzimpragos
Application debug in FPGAs in the presence of multiple asynchronous clocks. 189-192 - Nandeesha Veeranna, Benjamin Carrión Schäfer:
Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs. 193-196 - Shengjia Shao, Oskar Mencer, Wayne Luk:
Dataflow design for optimal incremental SVM training. 197-200 - Tianqi Wang, Linlin Zheng, Xi Jin, Bo Peng, Chuanjun Wang:
FPGA acceleration of TreePM N-body simulations for Modified Newton Dynamics. 201-204 - Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
hCODE: An open-source platform for FPGA accelerators. 205-208 - Vincent Migliore, Maria Mendez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, Guy Gogniat
Fast polynomial arithmetic for Somewhat Homomorphic Encryption operations in hardware with Karatsuba algorithm. 209-212 - Jorge Echavarria
FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. 213-216 - Naoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano:
Variable pipeline structure for Coarse Grained Reconfigurable Array CMA. 217-220 - Otávio Alcântara de Lima Jr., Weslley N. Costa, Virginie Fresse, Frédéric Rousseau:
A survey of NoC evaluation platforms on FPGAs. 221-224 - Tze Hon Tan
A modular architecture for dynamically reconfigurable middlebox with customized reconfiguration handler. 225-228 - Ali Asghar, Muhammad Mazher Iqbal
Exploring shared SRAM tables among NPN equivalent large LUTs in SRAM-based FPGAs. 229-232 - Naifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He, Zhigang Mao:
Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. 233-236 - Sumedh Guha, Wen Wang, Shafeeq Ibraheem, Mahesh Balakrishnan, Jakub Szefer:
Design and implementation of open-source SATA III core for Stratix V FPGAs. 237-240 - Ayesha Khalid, James Howe, Ciara Rafferty, Máire O'Neill:
Time-independent discrete Gaussian sampling for post-quantum cryptography. 241-244 - Qi Zhan, Min Gao, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang:
High performance Deformable Part Model accelerator based on FPGA. 245-248 - Taito Manabe, Yuichiro Shibata, Kiyoshi Oguri:
FPGA implementation of a real-time super-resolution system using a convolutional neural network. 249-252 - Zhenxue He, Limin Xiao, Longbing Zhang, Fei Gu, Zhisheng Huo, Mingfa Zhu, Li Ruan, Rui Liu, Xiang Wang:
EMA-FPRMs: An efficient minimization algorithm for fixed polarity Reed-Muller expressions. 253-256 - Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data. 257-260 - Maolin Wang, Ho-Cheung Ng, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Kevin K. Tsia
Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. 261-264 - Roberto DiCecco, Griffin Lacey, Jasmina Vasiljevic, Paul Chow, Graham W. Taylor, Shawki Areibi:
Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks. 265-268 - Li Ding, Ping Kang, Wenbo Yin, Linli Wang:
Hardware TCP Offload Engine based on 10-Gbps Ethernet for low-latency network communication. 269-272 - Yuzhi Zhou, Xi Jin, Tian Xiang:
Fixed-ratio DXT format Frame Buffer Compressor for mobile graphics systems. 273-276 - Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura
A memory-based realization of a binarized deep convolutional neural network. 277-280 - Lester Kalms, Ahmed Elhossini, Ben H. H. Juurlink:
FPGA based hardware accelerator for KAZE feature extraction algorithm. 281-284 - Song Xu, Qiang Liu, Tao Li, Hongxiang Fan:
IC security evaluation against fault injection attack based on FPGA emulation. 285-288 - Hiroki Nakahara, Akira Jinguji, Tomonori Fujii, Simpei Sato:
An acceleration of a random forest classification using Altera SDK for OpenCL. 289-292
Ph.D. Forum
- Jakub Podivinsky, Ondrej Cekan
Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs. 293-294 - Ondrej Cekan
Random stimuli generation based on a stochastic context-free grammar. 295-296 - Martin Krcma, Zdenek Kotásek, Jakub Lojda:
Implementation of fault tolerant techniques into FPNNs. 297-298 - Mengjun Li, Yongxin Zhu, Xu Wang, Tian Huang
Evaluation of variable precision computing with variable precision FFT implementation on FPGA. 299-300 - Jakub Lojda, Jakub Podivinsky, Martin Krcma, Zdenek Kotásek:
HLS-based fault tolerance approach for SRAM-based FPGAs. 301-302
Demo
- Lin Li, Quansheng Yang:
SMCFA: A Zynq-based stacked multi CPU-FPGA architecture. 303-306 - Zhehao Li, Jifang Jin, Lingli Wang, Ji Yang, Jiahua Lu:
A moving object extraction and classification system based on Zynq and IBM SuperVessel. 307-310 - Junying Chen, Shunfeng Zhou, Huaqing Min:
Implementation of parallel medical ultrasound imaging algorithm on CAPI-enabled FPGA. 311-314 - Xinyu Chen, Yong Gu, Chenxu Wang, Xuguang Guan:
Asymmetric multiprocessing for motion control based on Zynq SoC. 315-318
Design Competition
- Donald G. Bailey
Identification of Trax threats using pattern matching. 319-322 - Hiroshi Nakahara, Tetsui Ohkubo, Hideki Shimura, Ryotaro Sakai, Chiharu Tsuruta, Takahiro Kaneda, Hideharu Amano:
Trax solver on Zynq using incremental update algorithm. 323-326 - Akira Kojima:
Trax player implementation on FPGA using high level synthesis tool. 327-330
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