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FPT 2004: Brisbane, Australia
- Oliver Diessel, John Williams:
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, December 6-8, 2004. IEEE 2004
Keynote Papers
- Eric Keller, Gordon J. Brebner
:
Programming a hyper-programmable architecture for networked systems. 1-8 - Adrian Stoica, Didier Keymeulen, Tughrul Arslan, Vu Duong, Ricardo Salem Zebulum, Ian Ferguson, Xin Guo:
Self-recovery experiments in extreme environments using a field programmable transistor array. 9-15
Stream Processing
- Lingyan Sun, B. V. K. Vijaya Kumar
Field programmable gate array implementation of a generalized decoder for structured low-density parity check codes. 17-24 - Peter Sutton:
Partial character decoding for improved regular expression matching in FPGAs. 25-32
Programmable Architectures 1
- Steven J. E. Wilton, Noha Kafafi, Bingfeng Mei, Serge Vernalde:
Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays. 33-40 - Guy Lemieux, Edmund Lee, Marvin Tom, Anthony J. Yu:
Directional and single-driver wires in FPGA interconnect. 41-48 - Helia Naeimi, André DeHon:
A greedy algorithm for tolerating defective crosspoints in nanoPLA design. 49-56
CAD: Synthesis, Place and Route
- R. Manimegalai, B. Jayaram, A. Manoj Kumar, V. Kamakoti:
SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis. 57-64 - Tony Wong, Steven J. E. Wilton:
Placement and routing for non-rectangular embedded programmable logic cores in SoC design. 65-72 - Song Li, Carl Ebeling:
QuickRoute: a fast routing algorithm for pipelined architectures. 73-80
Application Accelerators
- C. K. Wong, K. K. Lo, Philip Heng Wai Leong:
An FPGA-based Othello endgame solver. 81-88 - Nozomu Nagata, Tsutomu Maruyama:
Real-time detection of line segments using the line Hough transform. 89-96 - Christopher Pohl, Marc Franzmeier, Mario Porrmann, Ulrich Rückert:
gNBX - reconfigurable hardware acceleration of self-organizing maps. 97-104
Evolvable and Adaptive Hardware
- Cristina Costa Santini, José F. M. do Amaral, Marco Aurélio Cavalcanti Pacheco, Ricardo Tanscheit:
Evolvability and reconfigurability. 105-112 - Justin Lee, Joaquin Sitte:
A gate-level model for morphogenetic evolvable hardware. 113-119
Programmable Architectures 2
- E. Syam Sundar Reddy, Vikram Chandrasekhar
A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. 121-128 - Andy Gean Ye, Jonathan Rose:
Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits. 129-136 - Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima:
Stream applications on the dynamically reconfigurable processor. 137-144
Mapping Techniques
- Nastaran Baradaran, Joonseok Park, Pedro C. Diniz:
Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks. 145-152 - Tim Todman
Memory optimisations for high-resolution imaging. 153-160 - Usama Malik, Oliver Diessel:
On the placement and granularity of FPGA configurations. 161-168
Arithmetic
- Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk:
Adaptive range reduction for hardware function evaluation. 169-176 - Ray C. C. Cheung, Ashley Brown, Wayne Luk, Peter Y. K. Cheung:
A scalable hardware architecture for prime number validation. 177-184 - Máire McLoone, Ciaran McIvor, John V. McCanny:
Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication. 185-191
Reconfigurable Systems
- John Williams
Programmable parallel coprocessor architectures for reconfigurable system-on-chip. 193-200 - Mariam Reeny George, Weng-Fai Wong:
Windows CE for a reconfigurable system-on-a-chip processor. 201-207 - Hidetomo Shibamura, Masayuki Fukuyama, Daisuke Uchida, Seiji Ikeda, Morihiro Kuga, Toshinori Sueyoshi:
EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA. 209-216
Design Flows
- Russell Klein, Rajat Moona:
Migrating software to hardware on FPGAs. 217-224 - Shawn Malhotra, Terry P. Borer, Deshanand P. Singh, Stephen Dean Brown:
The Quartus University Interface Program: enabling advanced FPGA research. 225-230 - Lesley Shannon, Paul Chow:
Maximizing system performance: using reconfigurability to monitor system communications. 231-238
Compilation
- Markus Weinhardt, Martin Vorbach, Volker Baumgarten, Frank May:
Using function folding to improve silicon efficiency of reconfigurable arithmetic arrays. 239-245 - Kenneth N. Macpherson, Robert W. Stewart:
Low FPGA area multiplier blocks for full parallel FIR filters. 247-254 - Henry Styles, David B. Thomas, Wayne Luk:
Pipelining designs with loop-carried dependencies. 255-262
Cryptography
- Sashisu Bajracharya, Deapesh Misra, Kris Gaj, Tarek A. El-Ghazawi:
Reconfigurable hardware implementation of mesh routing in number field sieve factorization. 263-270 - Omar Nibouche, Mokhtar Nibouche, Ahmed Bouridane, Ammar Belatreche:
Fast architectures for FPGA-based implementation of RSA encryption algorithm. 271-278 - Francis M. Crowe, Alan Daly, Tim Kerins, William P. Marnane:
Single-chip FPGA implementation of a cryptographic co-processor. 279-285
Poster Session
- José Luis Imaña:
Reconfigurable implementation of bit-parallel multipliers over GF(2m) for two classes of finite fields. 287-290 - Matthew J. W. Savage, Zoran A. Salcic, George G. Coghill, Grant Covic:
Extended genetic algorithm for codesign optimization of DSP systems in FPGAs. 291-294 - Zhen Liu, Kai Zheng, Bin Liu:
FPGA implementation of hierarchical memory architecture for network processors. 295-298 - Peter Waldeck, Neil W. Bergmann:
Evaluating software and hardware implementations of signal-processing tasks in an FPGA. 299-302 - Kimmo Järvinen, Matti Tommiska, Jorma Skyttä:
A scalable architecture for elliptic curve point multiplication. 303-306 - Cade C. Wells, Ed Duncan, David Renshaw:
An FPGA based prototyping platform for imager-on-chip applications. 307-310 - Daniel Denning, James Irvine
Compact iterative FPGA Camellia algorithm implementations. 311-314 - Xiang-Ju Qin, Ming-Cheng Zhu, Zhong-Yi Wei, Du Chao:
An adaptive Viterbi decoder based on FPGA dynamic reconfiguration technology. 315-318 - Sunil Shukla, Neil W. Bergmann:
Single bit error correction implementation in CRC-16 on FPGA. 319-322 - T. S. Ganesh, T. S. B. Sudarshan, Naveen Kumar Srinivasan, Karthick Jayapal:
Pre-silicon prototyping of a unified hardware architecture for cryptographic manipulation detection codes. 323-326 - Dzmitry Stsepankou, Klaus Kornmesser, Jürgen Hesser, Reinhard Männer:
FPGA-acceleration of cone-beam reconstruction for the X-ray CT. 327-330 - Tien-Lung Lee, Andy Lee, Neil W. Bergmann:
Interface adaptor logic - a new model for interfacing peripherals in IP based designs. 331-334 - T. Salim, John C. Devlin, Jim Whittington:
FPGA implementation of digital upconversion using distributed arithmetic FIR filters. 335-338 - T. Salim, John C. Devlin, Jim Whittington:
FPGA implementation of a phased array DBF using polyphase filters. 339-342 - Grace Elias, Ali Miri, Tet Hin Yeap:
FPGA design of HECC coprocessors. 343-346 - Yohei Hori
A tsume-shogi processor based on reconfigurable hardware. 347-350 - Md. Ashfaquzzaman Khan, Naoto Miyamoto, Takeshi Ohkawa, Amir Jamak, Soichiro Kita, Koji Kotani, Tadahiro Ohmi:
An approach to realize time-sharing of flip-flops in time-multiplexed FPGAs. 351-354 - John Hopf:
A parameterizable HandelC divider generator for FPGAs with embedded hardware multipliers. 355-358 - Noriyuki Aibe, Moritoshi Yasunaga:
Reconfigurable I/O interface for mobile equipments. 359-362 - Cheng Zhan, Sami Khawam, Tughrul Arslan:
Domain specific reconfigurable fabric targeting Viterbi algorithm. 363-366 - Joachim Becker, Yiannos Manoli:
A new architecture of field programmable analog arrays for reconfigurable instantiation of continuous-time filters. 367-370 - Jin Zhenyu, Mohit Sindhwani, Thambipillai Srikanthan:
RTOS acceleration on soft-core processors using instruction set customization. 371-374 - Nikolaus Voß, Thomas Eisenbach, Bärbel Mertsching:
A rapid prototyping framework for audio signal processing algorithms. 375-378 - Hisanori Fujisawa, Miyoshi Saito, Masaki Arai, Toshihiro Ozawa, Hideki Yoshizawa:
Cyclic reconfiguration for pipelined applications on coarse-grain reconfigurable circuits. 379-382 - Erik Schüler, Luigi Carro:
Achieving wide frequency range in an analog FPGA. 383-386 - Jung-Woo Kim, Jae-One Oh, Cheol-Ho Jeong, Jae-Hyun Kim:
3D graphics accelerator platform for mobile devices. 387-390 - Mehrdad Eslami Dehkordi, Stephen Dean Brown:
Retiming aware clustering for sequential circuits. 391-394 - Abdallah Merhebi, Otmane Aït Mohamed:
A scalable and pipelined FPGA implementation of an OC192 WF scheduler. 395-398 - Esam El-Araby, Tarek A. El-Ghazawi, Jacqueline Le Moigne, Kris Gaj:
Wavelet spectral dimension reduction of hyperspectral imagery on a reconfigurable computer. 399-402 - Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo
Architectures for ICT on FPGA. 403-406 - Pierre Chalimbaud, François Berry:
Design of an imaging system based on FPGA technology and CMOS imager. 407-411 - Heiko Kalte, Gareth Lee, Mario Porrmann, Ulrich Rückert:
Study on column wise design compaction for reconfigurable systems. 413-416 - John Xue, Peter Sutton:
Memory specification for reconfigurable computing synthesis tools. 417-420 - Lodewijk T. Smit, Gerard J. M. Smit, Johann L. Hurink, Hajo Broersma
Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture. 421-424 - Fariborz Fereydouni-Forouzandeh, Otmane Aït Mohamed:
An FPGA implementation of a modified version of RED algorithm. 425-428 - Hiroshi Kadota, Yoshiaki Hori, Akiyoshi Wakatani:
A new reconfigurable architecture with smart data-transfer subsystems for the intelligent image processing. 429-432 - Dirk Koch, Ali Ahmadinia, Christophe Bobda, Heiko Kalte:
FPGA architecture extensions for preemptive multitasking and hardware defragmentation. 433-436 - Gerard K. Rauwerda, Gerard J. M. Smit:
Implementation of a flexible RAKE receiver in heterogeneous reconfigurable hardware. 437-440 - Guerric Meurice de Dormale, Philippe Bulens, Jean-Jacques Quisquater:
An improved Montgomery modular inversion targeted for efficient implementation on FPGA. 441-444 - Raúl Mateos, José Luis Lázaro, Felipe Espinosa:
Hardware/software co-simulation environment for CSoC with soft processors. 445-448 - Stephen J. Bellis, Kafil Mahmood Razeeb, Chitta Ranjan Saha
FPGA implementation of spiking neural networks - an initial step towards building tangible collaborative autonomous agents. 449-452 - Esmail Chitalwala, Tarek A. El-Ghazawi, Kris Gaj, Nikitas A. Alexandridis, Daniel S. Poznanovic:
Effective system and performance benchmarking for reconfigurable computers. 453-456 - Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk:
Scalable structured data access by combining autonomous memory blocks. 457-460 - Stephen O'Kane, Sakir Sezer:
An investigation into the design of high-performance shared buffer architectures based on FPGA technology with embedded memory. 461-464 - Sami Khawam, Tughrul Arslan:
Switch-box design for synthesizable coarse-grain arrays for system-on-chip applications. 465-468
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