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FPGA 2021: Virtual Event, USA
- Lesley Shannon, Michael Adler:
FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28 - March 2, 2021. ACM 2021, ISBN 978-1-4503-8218-2
Session 1: FPGA Architecture
- Prashanth Mohan, Oguz Atli, Onur O. Kibar, V. Mohammed Zackriya, Larry T. Pileggi, Ken Mai:
Top-down Physical Design of Soft Embedded FPGA Fabrics. 1-10 - Morten B. Petersen, Stefan Nikolic
, Mirjana Stojilovic
NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs. 11-22 - Aman Arora
Tensor Slices to the Rescue: Supercharging ML Acceleration on FPGAs. 23-33 - Stefan Nikolic
Global Is the New Local: FPGA Architecture at 5nm and Beyond. 34-44 - Dirk Koch, Nguyen Dao, Bea Healy, Jing Yu, Andrew Attwood:
FABulous: An Embedded FPGA Framework. 45-56 - Martin Langhammer, Eriko Nurvitadhi, Bogdan Pasca
Stratix 10 NX Architecture and Applications. 57-67
Keynote 1
- Philip Harris:
Scientific Applications of FPGAs at the LHC. 68
Session 2: Abstractions and Tools
- Xinyu Chen, Hongshi Tan, Yao Chen
ThunderGP: HLS-based Graph Processing Framework on FPGAs. 69-80 - Licheng Guo, Yuze Chi, Jie Wang, Jason Lau
AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. 81-92 - Jie Wang, Licheng Guo, Jason Cong:
AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA. 93-104 - Alec Lu, Zhenman Fang, Weihua Liu, Lesley Shannon:
Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers through Microbenchmarking. 105-115 - Young-kyu Choi
HBM Connect: High-Performance HLS Interconnect for FPGA HBM. 116-126 - Ang Li
PRGA: An Open-Source FPGA Research and Prototyping Framework. 127-137 - Marco Antonio Merlini, Isamu Poy, Paul Chow:
Interactive Debugging at IP Block Interfaces in FPGAs. 138-144
Poster Session 1
- Jianyi Cheng, John Wickerson, George A. Constantinides:
Probabilistic Optimization for High-Level Synthesis. 145 - Bingyi Zhang, Rajgopal Kannan, Viktor K. Prasanna:
A Framework for Optimizing GCN Inference on FPGA. 145 - Dillon Huff, Steve Dai, Pat Hanrahan:
Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs. 145-146 - Behnam Ghavami, Seyed Milad Ebrahimi, Zhenman Fang, Lesley Shannon:
LEAP: A Deep Learning based Aging-Aware Architecture Exploration Framework for FPGAs. 146 - Gagandeep Singh, Dionysios Diamantopoulos, Juan Gómez-Luna, Sander Stuijk, Onur Mutlu, Henk Corporaal:
Modeling FPGA-Based Systems via Few-Shot Learning. 146 - Beilei Jiang
APCNN: Explore Multi-Layer Cooperation for CNN Optimization and Acceleration on FPGA. 146-147 - Chenhao Liu, Zhiyuan Shao, Kexin Li, Minkang Wu, Jiajie Chen, Ruoshi Li, Xiaofei Liao, Hai Jin:
ScalaBFS: A Scalable BFS Accelerator on FPGA-HBM Platform. 147 - Atefeh Sohrabizadeh, Cody Hao Yu, Min Gao, Jason Cong:
AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators. 147 - Yufei Ma, Gokul Krishnan, Yu Cao, Le Ye, Ru Huang:
SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA. 148 - Zewei Du, Yann Herklotz
Fuzzing High-Level Synthesis Tools. 148 - Qianfeng Clark Shen, Jun Zheng, Paul Chow:
RIFL: A Reliable Link Layer Network Protocol for FPGA-to-FPGA Communication. 148
Session 3: Machine Learning and Supporting Algorithms
- Qinggang Wang, Long Zheng, Yu Huang, Pengcheng Yao
GraSU: A Fast Graph Update Library for FPGA-based Dynamic Graph Processing. 149-159 - Martin Langhammer, Bogdan Pasca
Folded Integer Multiplication for FPGAs. 160-170 - Yichi Zhang
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations. 171-182 - Yuan Meng
DYNAMAP: Dynamic Algorithm Mapping Framework for Low Latency CNN Inference. 183-193 - Alireza Khodamoradi, Kristof Denolf, Ryan Kastner
S2N2: A FPGA Accelerator for Streaming Spiking Neural Networks. 194-205 - Qijing Huang
CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs. 206-216 - Martin Langhammer, Bogdan Pasca
Efficient FPGA Modular Multiplication Implementation. 217-223
Keynote 2
- Dan Werthimer:
Are We Alone? Searching for ET with FPGAs. 224
Poster Session 2
- Yicheng Zhang
Stealing Neural Network Structure through Remote FPGA Side-channel Analysis. 225 - Varun Sharma, Paul Chow:
Exploring PGAS Communication for Heterogeneous Clusters with FPGAs. 225 - Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong:
Extending High-Level Synthesis for Task-Parallel Programs. 225 - Ayokunle Fadamiro, Pouyan Rezaie, Spencer K. Millican, Christopher Harris:
Simulating and Evaluating a Quaternary Logic FPGA Based on Floating-gate Memories and Voltage Division. 226 - Lana Josipovic
Resource Sharing in Dataflow Circuits. 226 - Mahyar Emami, Endri Bezati, Jörn W. Janneck, James R. Larus:
Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems. 226-227 - Mustafa S. Gobulukoglu, Colin Drewes, Bill Hunter, Dustin Richmond
Classifying Computations on Multi-Tenant FPGAs. 227 - Hamza Khan, Asma Khan, Zainab Khan, Lun Bin Huang, Kun Wang, Lei He:
NPE: An FPGA-based Overlay Processor for Natural Language Processing. 227 - Sitao Huang, Kun Wu, Hyunmin Jeong, Chengyue Wang, Deming Chen, Wen-Mei Hwu:
PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow. 227-228 - Seyedramin Rasoulinezhad, David Boland, Philip H. W. Leong:
MLBlocks: FPGA Blocks for Machine Learning Applications. 228 - Shulin Zeng, Guohao Dai, Hanbo Sun, Jun Liu, Hongren Zheng
3M-AI: A Multi-task and Multi-core Virtualization Framework for Multi-FPGA AI Systems in the Cloud. 228
Session 4: Applications
- Ho-Cheung Ng, Izaak Coleman
Reconfigurable Acceleration of Short Read Mapping with Biological Consideration. 229-239 - Lukas Leuenberger
An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components. 240-250 - Davide Conficconi
A Framework for Customizable FPGA-based Image Registration Accelerators. 251-261 - Sahand Salamat, Armin Haj Aboutalebi, Behnam Khaleghi, Joo Hwan Lee, Yang-Seok Ki, Tajana Rosing:
NASCENT: Near-Storage Acceleration of Database Sort on SmartSSD. 262-272 - Peipei Zhou
MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators. 273-279 - Thomas Luinaud
Design Principles for Packet Deparsers on FPGAs. 280-286
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