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24th DAC 1987: Miami Beach, Florida, USA
- A. O'Neill, D. Thomas:
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987. IEEE Computer Society Press / ACM 1987 - L.-T. Wang, Nathan E. Hoover, Edwin H. Porter, John J. Zasio:
SSIM: A Software Levelized Compiled-Code Simulator. 2-8 - Randal E. Bryant, Derek L. Beatty, Karl S. Brace, Kyeongsoon Cho, Thomas J. Sheffler:
COSMOS: A Compiled Simulator for MOS Circuits. 9-16 - S. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter:
A Fast Signature Simulation Tool for Built-In Self-Testing Circuits. 17-25 - Nikrouz Faroughi, Michael A. Shanblatt:
An Improved Systematic Method for Constructing Systolic Arrays from Algorithms. 26-34 - Rajiv Jain, Alice C. Parker, Nohbyung Park:
Predicting Area-Time Tradeoffs for Pipelined Design. 35-41 - Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley:
A Prototype Framework for Knowledge-Based Analog Circuit Synthesis. 42-49 - Mely Chen Chi:
An Automatic Rectilinear Partitioning Procedure for Standard Cells. 50-55 - Lov K. Grover:
Standard Cell Placement Using Simulated Sintering. 56-59 - Ralph-Michael Kling, Prithviraj Banerjee:
ESP: A New Standard Cell Placement Package Using Simulated Evolution. 60-66 - V. Masurkar:
Requirements for a Practical Software Engineering Environment. 67-73 - Jonathan B. Rosenberg:
The Making of VIVID: A Software Engineering Perspective. 74-81 - Norman J. Elias:
A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator. 82-88 - Andrei Vladimirescu, David Weiss, Manolis Katevenis, Zvika Bronstein, Alon Kifir, Karja Danuwidjaja, K. C. Ng, Niraj Jain, Steven Lass:
A Vector Hardware Accelerator with Circuit Simulation Emphasis. 89-94 - M. T. Smith:
A Hardware Switch Level Simulator for Large MOS Circuits. 95-100 - Prathima Agrawal, William J. Dally, Ahmed K. Ezzat, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar:
Architecture and Design of the MARS Hardware Accelerator. 101-107 - Donald M. Webber, Alberto L. Sangiovanni-Vincentelli:
Circuit Simulation on the Connection Machine. 108-113 - Kye S. Hedlund:
Aesop: A Tool for Automated Transistor Sizing. 114-120 - Mehmet A. Cirit:
Transistor Sizing in CMOS Circuits. 121-124 - Mark Hofmann, Jae K. Kim:
Delay Optimization of Combinational Static CMOS Logic. 125-132 - Robert E. Canright, A. R. Helland:
Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic. 133-139 - J. Royle, Mikael Palczewski, H. VerHeyen, N. Naccache, Jiri Soukup:
Geometrical Compaction in One Dimension for Channel Routing. 140-145 - D. B. Polkl:
A Three-Layer Gridless Channel Router with Compaction. 146-151 - H. H. Chen:
Routing L-Shaped Channels in Nonslicing-Structure Placement. 152-158 - Nicholas J. Naclerio, Sumio Masuda, Kazuo Nakajima:
Via Minimization for Gridless Layouts. 159-165 - Louise Trevillyan:
An Overview of Logic Synthesis Systems. 166-172 - Wojciech Maly:
Realistic Fault Modeling for VLSI Testing. 173-180 - Steven P. Smith, M. Ray Mercer, B. Brodk:
Demand Driven Simulation: BACKSIM. 181-187 - J. W. Smith, K. S. Smith, Robert J. Smith:
Faster Architectural Simulation Through Parallelism. 189-194 - Pierre G. Paulin, John P. Knight:
Force-Directed Scheduling in Automatic Data Path Synthesis. 195-202 - Forrest Brewer
, Daniel Gajski:
Knowledge Based Control in Micro-Architecture Design. 203-209 - Fadi J. Kurdahi, Alice C. Parker:
REAL: a program for REgister ALlocation. 210-215 - R. K. McGehee:
A Practical Moat Router. 216-222 - S. Chowdhury:
An Automated Design of Minimum-Area IC Power/Ground Nets. 223-229 - Steven T. Healey, William J. Kubitz:
Abstract Routing of Logic Networks for Custom Module Generation. 230-236 - Michael H. Schultz, Franc Brglez:
Accelerated Transition Fault Simulation. 237-243 - Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana:
On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates. 244-250 - S. E. Concina, G. S. Liu:
Integrating Design Information for IC Diagnosis. 251-257 - Robert M. McDermott, David Stern:
Switch Directed Dynamic Causal Networks - a Paradigm for Electronic System Diagnosis. 258-264 - Daniel Weise:
Functional Verification of MOS Circuits. 265-270 - Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton:
On the Verification of Sequential Machines at Differing Levels of Abstraction. 271-276 - Mandalagiri S. Chandrasekhar, J. P. Privitera, K. W. Conradt:
Application of Term Rewriting Techniques to Hardware Design Verification. 277-282 - Hi-Keung Tony Ma, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli, Ruey-Sing Wei:
Logic Verification Algorithms and Their Parallel Implementation. 283-290 - Clyde W. Carpenter, Mark Horowitz:
Generating Incremental VLSI Compaction Spacing Constraints. 291-297 - Xiao-Ming Xiong, Ernest S. Kuh:
Nutcracker: An Efficient and Intelligent Channel Spacer. 298-304 - Lars S. Nyland, Stephen W. Daniel, C. Durward Rogers:
Improving Virtual-Grid Compaction Through Grouping. 305-310 - Bill Lin, A. Richard Newton:
KAHLUA: A Hierarchical Circuit Disassembler. 311-317 - Bryan Preas:
Benchmarks for Cell-Based Layout Systems. 319-320 - Rajiv Bhateja, Randy H. Katz:
VALKYRIE: A Validation Subsystem of a Version Server for Computer-Aided Design Data. 321-327 - Arnon Rosenthal, Sandra Heiler:
Querying Part Hierarchies: A Knowledge-Based Approach. 328-334 - Sandra Heiler, Umeshwar Dayal, Jack A. Orenstein, Susan Radke-Sproull:
An Object-Oriented Approach to Data Management: Why Design Databases Need It. 335-340 - Kurt Keutzer:
DAGON: Technology Binding and Local Optimization by DAG Matching. 341-347 - Jared A. Beekman, Robert Michael Owens, Mary Jane Irwin:
Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation. 357-362 - Steven J. Friedman, Kenneth J. Supowit:
Finding the Optimal Variable Ordering for Binary Decision Diagrams. 358-356 - J. Apte, Gershon Kedem:
Strip Layout: A New Layout Methodology for Standard Circuit Modules. 363-369 - Johannes Schuck, Norbert Wehn, Manfred Glesner, G. Kamp:
The ALGIC Silicon Compiler System: Implementation, Design Experience and Results. 370-375 - Wayne Wei-Ming Dai, Masao Sato, Ernest S. Kuh:
A Dynamic and Efficient Representation of Building-Block Layout. 376-384 - Chun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya:
BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays. 385-391 - Hans-Joachim Wunderlich:
On Computing Optimized Input Probabilities for Random Tests. 392-398 - Philip S. Yu, C. Mani Krishna, Yann-Hang Lee:
VLSI Circuit Testing Using an Adaptive Optimization Model. 399-406 - Andrzej Krasniewski, Slawomir Pilarski:
Circular Self-Test Path: A Low-Cost BIST Technique. 407-415 - John J. Granacki Jr., Alice C. Parker:
PHRAN-SPAN: A Natural Language Interface for System Specifications. 416-422 - William Lee, Gerald Liu, Kevin Peterson:
TED: A Graphical Technology Description Editor. 423-428 - William Lee:
"?": A Context-Sensitive Help System Based on Hypertext. 429-435 - Robert K. Chun, Keh-Jeng Chang, Lawrence P. McNamee:
VISION: VHDL Induced Schematic Imaging on Net-Lists. 436-442 - D. L. Johannsen, S. K. Tsubota, Kenneth S. McElvain
An Intelligent Compiler Subsystem for a Silicon Compiler. 443-450 - Bertrand Serlet:
Fast, Small, and Static Combinatorial CMOS Circuits. 451-458 - P. A. Subrahmanyam:
LCS - A Leaf Cell Synthesizer Employing Formal Deduction Techniques. 459-465 - John S. J. Chen, David Y. Chen:
A Design Rule Independent Cell Compiler. 466-471 - Moe Shahdad:
An Interface between VHDL and EDIF. 472-478 - Curtis H. Parks:
Tutorial: Reading and Reviewing the Common Schema for Electrical Design and Analysis. 479-483 - Larry F. Saunders:
The IBM VHDL Design System. 484-490 - J. Hines:
Where VHDL Fits Within the CAD Environment. 491-494 - Susheel J. Chandra, Janak H. Patel:
A Hierarchical Approach Test Vector Generation. 495-501 - Tom E. Kirkland, M. Ray Mercer:
A Topological Search Algorithm for ATPG. 502-508 - M. Ladjadj, John F. McDonald:
Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits. 509-515 - Robert Michael Owens, Mary Jane Irwin:
An Overview of the Penn State Design System. 516-522 - Shigenobu Suzuki, Tatsushige Bitoh, Masao Kakimoto, Kazutoshi Takahashi, Takao Sugimoto:
TRIP: An Automated Technology Mapping System. 523-529 - Takuji Ogihara, H. Toyoshima, Shinichi Murai:
ASTA: LSI Design Management System. 530-536 - D. F. Wong
Array Optimization for VLSI Synthesis. 537-543 - R. L. Maiasz, John P. Hayes:
Layout Optimization of CMOS Functional Cells. 544-551 - Y.-C. Chang, S. C. Chang, L.-H. Hsu:
Automated Layout Generation Using Gate Matrix Approach. 552-558 - Ronald Waxman:
The Design Automation Standards Environment. 559-561 - L. O'Connell:
Design Automation Standards Need Integration. 562-562 - Roger J. Pachter:
Design Automation Standards - Perspectives from a Down-the-Road End User. 563-564 - M. L. Brei:
Needed: A Meta-Language for Evaluating the Expressiveness of EDIF, IGES, VHDL and Other Representation Mechanisms. 565-565 - Shun-Lin Su, Vasant B. Rao, Timothy N. Trick:
HPEX: A Hierarchical Parasitic Circuit Extractor. 566-569 - Don Stark, Mark Horowitz:
RED: Resistance Extraction for Digital Simulation. 570-573 - Jung-Gen Wu, William P.-C. Ho, Yu Hen Hu, David Y. Y. Yun, H. J. Yu:
Function Search from Behavioral Description of a Digital System. 574-579 - Christopher Kingsley:
The Implementation of a State Machine Compiler. 580-583 - Edward P. Stabler, Haluk Bingol:
Boolean Comparison by Simulation. 584-587 - Larry Soulé, R. Blank:
Statistics for Parallelism and Abstraction Level in Digital Simulation. 588-591 - Steven S. Leung, Michael A. Shanblatt:
A Conceptual Framework for Designing ASIC Hardware. 592-595 - Dick C. A. Bulterman:
CASE: An Integrated Design Environment for Algorithm-Driven Architectures. 596-599 - R. Galivanche, Sudhakar M. Reddy:
A Parallel PLA Minimization Program. 600-607 - Chidchanok Lursinsap, Daniel Gajski:
Improving a PLA Area by Pull-Up Transistor Folding. 608-614 - L. B. Nguyen, M. A. Perkowdki, N. B. Goldstein:
PALMINI - Fast Boolean Minimizer for Personal Computers. 615-621 - Chin-Long Wey:
On Yield Consideration for the Design of Redundant Programmable Logic Arrays. 622-628 - David Kaplan:
Routing with a Scanning Window-8Ma Unified Approach. 629-632 - Charles H. Ng:
A "gridless" Variable-Width Channel Router for Marco Cell Design. 633-636 - Richard J. Enbody, Hung-Chang Du:
General Purpose Router. 637-640 - Y. C. Hsu, Y. Pan, William J. Kubitz:
A Path Selection Global Router. 641-644 - P. C. Shah, Hosaker N. Mahabala:
A New Compaction Scheme Based on Compression Ridges. 645-648 - Bernd Becker
Hierarchical Design Based on a Calculus of Nets. 649-653 - E. F. M. Kouka, Gabriele Saucier:
An Application of Exploratory Data Analysis Techniques to Floorplan Design. 654-658 - Wen-Jeng Lue, Lawrence P. McNamee:
PLAY: Pattern-Based Symbolic Cell Layout: Part I: Transistor Placement. 659-665 - T. Cesear, E. Iodice, C. Tsareff:
PAMS: An Expert System for Parameterized Module Synthesis. 666-671 - Youn-Long Lin, Daniel Gajski:
LES: A Layout Expert System. 672-678 - Robin L. Steele:
An Expert System Application in Semicustom VLSI Design. 679-688 - Pinaki Mazumder, Janak H. Patel, W. Kent Fuchs:
Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories. 689-694 - Balakrishnan Krishnamurthy:
A Dynamic Programming Approach to the Test Point Insertion Problem. 695-705 - D. Praizler, G. Fritz:
A Parts Selection Expert System to Increase Manufacturability. 706-712 - J. Y. Tou, W. H. Ki, K. C. Fan, C. L. Huang:
Knowledge Based Approach for the Verification of CAD Database Generated by an Automated Schematic Capture System. 713-720 - Eric Rosenberg:
A New Interactive Supply/Demand Router with Rip-Up Capability for Printed Circuit Boards. 721-726 - Jeremy Dion:
Fast Printed Circuit Board Routing. 727-734 - R. Forbes:
Heuristic Acceleration of Force-Directed Placement. 735-740 - J. D. Morison, N. E. Peeling, T. L. Thorp, E. V. Whiting:
EASE: A Design Support Environment for the HDDL ELLA. 741-749 - Louis-Philippe Demers
CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools. 750-756 - Emil F. Girczyc, Tai A. Ly:
STEM: An IC Design Environment Based on the Smalltalk Model-View-Controller Construct. 757-763 - Anthony J. Gadient, J. L. Ebel:
Rational for and Organization of the Engineering Information System Program. 764-769 - Ali A. Minai, Ronald D. Williams, F. W. Blake:
A Discrete Heuristics Approach to Predictive Evaluation of Semi-Custom IC Layouts. 770-776 - Gotaro Odawara, T. Hamuro, Kazuhiko Iijima, T. Yoshino, Y. Dai:
A Rule-Based Placement System for Printed Wiring Boards. 777-785 - Ching-Farn Eric Wu, Anthony S. Wojcik, Lionel M. Ni:
A Rule-Based Circuit Representation for Automated CMOS Design and Verification. 786-792 - T. D. Spiers, D. A. Edwards:
A High Performance Routing Engine. 793-799 - Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq:
A Hardware Accelerator for Maze Routing. 800-806 - Mark Jones, Prithviraj Banerjee:
Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube. 807-813 - Kunle Olukotun, Trevor N. Mudge:
A Preliminary Investigation into Parallel Routing on a Hypercube Computer. 814-820 - Richard H. Lathrop, Robert J. Hall, Robert S. Kirk:
Functional Abstraction from Structure in VLSI Simulation Models. 822-828 - S. Koeppe:
Optimal Layout to Avoid CMOS Stuck-Open Faults. 829-835
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