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42nd MICRO 2009: New York, NY, USA
- David H. Albonesi, Margaret Martonosi, David I. August, José F. Martínez:
42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA. ACM 2009, ISBN 978-1-60558-798-1
Keynote 1
- Balaram Sinharoy:
POWER7 multi-core processor design. 1
Memory system
- Wangyuan Zhang, Tao Li:
Characterizing and mitigating the impact of process variations on phase change based memory systems. 2-13 - Moinuddin K. Qureshi, John P. Karidis, Michele Franceschini, Vijayalakshmi Srinivasan, Luis A. Lastras, Bülent Abali:
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. 14-23 - Laura M. Grupp, Adrian M. Caulfield
, Joel Coburn, Steven Swanson
Characterizing flash memory: anomalies, observations, and applications. 24-33 - George L. Yuan, Ali Bakhoda, Tor M. Aamodt:
Complexity effective memory access scheduling for many-core accelerator architectures. 34-44
Optimization
- Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim:
Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping. 45-55 - Changhee Jung, Nathan Clark:
DDT: design and evaluation of a dynamic program analysis for optimizing data structure usage. 56-66 - Hongbo Rong:
Tree register allocation. 67-77 - Christophe Dubach, Timothy M. Jones
Portable compiler optimisation across embedded programs and microarchitectures using machine learning. 78-88
Fault tolerance
- Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu:
Improving cache lifetime reliability at ultra-low voltages. 89-99 - Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke:
ZerehCache: armoring cache architectures in high defect density technologies. 100-110 - Jaume Abella
Low Vccmin fault-tolerant cache with highly predictable performance. 111-121 - Siva Kumar Sastry Hari, Man-Lap Li, Pradeep Ramachandran, Byn Choi, Sarita V. Adve:
mSWAT: low-cost hardware fault detection and diagnosis for multicore systems. 122-132
Transactional memory/memory consistency
- Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Torrellas, Jae-Woo Lee, Xing Fang, Samuel P. Midkiff
BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support. 133-144 - Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach
EazyHTM: eager-lazy hardware transactional memory. 145-155 - Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge:
Proactive transaction scheduling for contention management. 156-167
Power
- Alex Shye, Benjamin Scholbrock, Gokhan Memik:
Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures. 168-178 - Mahesh Ketkar, Eli Chiprout:
A microarchitecture-based framework for pre- and post-silicon power delivery analysis. 179-188 - Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen
Reducing peak power with a table-driven adaptive processor core. 189-200
3D/caches
- Gabriel H. Loh:
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy. 201-212 - Alejandro Valero
An hybrid eDRAM/SRAM macrocell to implement first-level data caches. 213-221 - Bo Zhao, Yu Du, Youtao Zhang, Jun Yang:
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor. 222-231
On-chip networks
- Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha:
In-network coherence filtering: snoopy coherence without broadcasts. 232-243 - Mitchell Hayenga, Natalie D. Enright Jerger
SCARAB: a single cycle adaptive routing and bufferless network. 244-254 - John Kim
Low-cost router microarchitecture for on-chip networks. 255-266
Keynote 2
- Mark Horowitz:
Why design must change: rethinking digital design. 267
On-chip networks
- Boris Grot
Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip. 268-279 - Reetuparna Das
Application-aware prioritization mechanisms for on-chip networks. 280-291 - Asit K. Mishra, Reetuparna Das
A case for dynamic frequency tuning in on-chip networks. 292-303 - Dana Vantrease, Nathan L. Binkert, Robert Schreiber, Mikko H. Lipasti:
Light speed arbitration and flow control for nanophotonic interconnects. 304-315
Memory systems
- Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt:
Coordinated control of multiple prefetchers in multi-core systems. 316-326 - Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt:
Improving memory bank-level parallelism in the presence of prefetching. 327-336 - Ciji Isen, Lizy Kurian John:
ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem. 337-346 - Sangyeun Cho, Hyunjin Lee:
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance. 347-357
Reconfigurability/security
- Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz:
Using a configurable processor generator for computer architecture prototyping. 358-369 - Hyunchul Park, Yongjun Park, Scott A. Mahlke:
Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications. 370-380 - Hari Kannan:
Ordering decoupled metadata accesses in multiprocessors. 381-390 - Haibo Chen, Liwei Yuan, Xi Wu, Binyu Zang, Bo Huang
Control flow obfuscation with information flow tracking. 391-400
Caches
- Mainak Chaudhuri:
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches. 401-412 - Daniel Hackenberg
Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems. 413-422 - Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos:
A tagless coherence directory. 423-434
Variations/power
- Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David M. Brooks:
Tribeca: design for PVT variations with local recovery and fine-grained adaptation. 435-446 - Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas:
The BubbleWrap many-core: popping cores for sequential acceleration. 447-458 - Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser:
Multiple clock and voltage domains for chip multi processors. 459-468
Potpourri
- Sheng Li, Jung Ho Ahn
McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. 469-480 - Vladimir Cakarevic, Petar Radojkovic
Characterizing the resource-sharing levels in the UltraSPARC T2 processor. 481-492 - Mohit Tiwari
Execution leases: a hardware-supported mechanism for enforcing strong non-interference. 493-504
Caches
- Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk:
Optimizing shared cache behavior of chip multiprocessors. 505-516 - Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang:
SHARP control: controlled shared cache management in chip multiprocessors. 517-528 - Dyer Rolán, Basilio B. Fraguela
Adaptive line placement with the set balancing cache. 529-540
Debugging
- Adrian Nistor, Darko Marinov, Josep Torrellas:
Light64: lightweight hardware support for data race detection during systematic testing of parallel programs. 541-552 - Brandon Lucia, Luis Ceze:
Finding concurrency bugs with context-aware communication graphs. 553-563 - Dongyoon Lee
Offline symbolic analysis for multi-processor execution replay. 564-575 - Gilles Pokam, Cristiano Pereira, Klaus Danne, Rolf Kassa, Ali-Reza Adl-Tabatabai:
Architecting a chunk-based memory race recorder in modern CMPs. 576-585
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