Search Results (1,247)

On-chip gene synthesis has the potential to improve the synthesis throughput and reduce the cost exponentially. While there exist several microarray-based oligo synthesis technologies, on-chip gene assembly has yet to be demonstrated. This work introduces a novel on-chip DNA assembly method via dielectrophoresis (DEP) that can potentially be integrated with microarray-based oligo synthesis on the same chip. Our DEP chip can selectively manipulate oligos and guide their movement without perturbing the surrounding fluid medium, thus aiding in DNA assembly. Helical forked electrode design has been optimized for compatibility with DEP, ensuring efficient control over target oligos. By applying an alternating current signal set at 2 MHz, we successfully achieve the desired directed movement of oligonucleotides. Additionally, chemical treatments combined with photoirradiation enabled the connection of complementary gene sequences and the subsequent release of single-stranded DNA products. Sequencing results validate the effective assembly of DNA fragments, approximately 500 base pairs in length, using our DEP device. Full article

Background/Objectives: Hydrophobic microparticles are one of the most versatile structures in drug delivery and tissue engineering. These constructs offer a protective environment for hydrophobic or water-sensitive compounds (e.g., drugs, peroxides), providing an optimal solution for numerous biomedical purposes, such as drug delivery or oxygen therapeutics. The intravascular administration of hydrophobic microparticles requires a safe-to-flow particle profile, which typically corresponds to a maximum size of 5 µm—the generally accepted diameter for the thinnest blood vessels in humans. However, the production of hydrophobic microparticles below this size range remains largely unexplored. In this work, we investigate the fabrication of hydrophobic microparticles at safe-to-inject and safe-to-flow sizes (<5 µm) for intravascular administration. Methods: Polycaprolactone microparticles (PCL MPs) are produced using a double-emulsification method with tip ultrasonication, for which various production parameters (PCL molecular weight, PCL concentration, type of stabilizer, and filtration) are optimized to obtain particles at sizes below 5 µm. Results: We achieve a PCL MP size distribution of 99.8% below this size limit, and prove that these particles can flow without obstruction through a microfluidic model emulating a thin human blood capillary (4.1 µm × 3.0 µm width × heigh). Conclusions: Overall, we demonstrate that hydrophobic microparticles can be fabricated at safe-to-flow sizes using a simple and scalable setup, paving the way towards their applicability as new intravascular injectables. Full article

The integration of a photodetector that converts optical signals into electrical signals is essential for scalable integrated lithium niobate photonics. Two-dimensional materials provide a potential high-efficiency on-chip detection capability. Here, we demonstrate an efficient on-chip photodetector based on a few layers of MoTe₂ on a thin film lithium niobate waveguide and integrate it with a microresonator operating in an optical telecommunication band. The lithium-niobate-on-insulator waveguides and micro-ring resonator are fabricated using the femtosecond laser photolithography-assisted chemical–mechanical etching method. The lithium niobate waveguide-integrated MoTe₂ presents an absorption coefficient of 72% and a transmission loss of 0.27 dB µm⁻¹ at 1550 nm. The on-chip photodetector exhibits a responsivity of 1 mA W⁻¹ at a bias voltage of 20 V, a low dark current of 1.6 nA, and a photo–dark current ratio of 10⁸ W⁻¹. Due to effective waveguide coupling and interaction with MoTe₂, the generated photocurrent is approximately 160 times higher than that of free-space light irradiation. Furthermore, we demonstrate a wavelength-selective photonic device by integrating the photodetector and micro-ring resonator with a quality factor of 10⁴ on the same chip, suggesting potential applications in the field of on-chip spectrometers and biosensors. Full article

The practical implementation of terahertz (THz) imaging and spectroscopic systems in real operational conditions requires them to be of a compact size, to have enhanced functionality, and to be user-friendly. This work demonstrates the single-sided integration of Fresnel-zone-plate-based optical elements with InGaAs bow-tie diodes directly on a semiconductor chip. Numerical simulations were conducted to optimize the Fresnel zone plate’s focal length and the InP substrate’s thickness to achieve constructive interference at 600 GHz, room-temperature operation and achieve a sensitivity more than an order of magnitude higher—up to 24.5 V/W—than that of a standalone bow-tie detector. Investigations revealed the strong angular dependence of the incident radiation on the Fresnel zone plate-integrated bow-tie diode’s response. These findings pave a promising avenue for the further development of single-sided integration of flat optics with THz detectors, enabling improved sensitivity, simplified manufacturing processes, and reduced costs for THz detection systems in a more compact design scheme. Full article

Physically unclonable functions (PUFs) represent emerging cryptographic primitives that exploit the uncertainty of the CMOS manufacturing process as an entropy source for generating unique, random and stable keys. These devices can be potentially used in a wide variety of applications ranging from secret key generation, anti-counterfeiting, and low-cost authentications to advanced protocols such as oblivious transfer and key exchange. Unfortunately, guaranteeing adequate PUF stability is still challenging, thus often requiring post-silicon stability enhancement techniques. The latter help to contrast the raw sensitivity to on-chip noise and variations in the environmental conditions (i.e., voltage and temperature variations), but their area and energy costs are not always feasible for IoT devices that operate with constrained budgets. This pushes the demand for ever more stable, area- and energy-efficient solutions at design time. This review aims to provide an overview of several weak PUF solutions implemented in CMOS technology, discussing their performance and suitability for being employed in security applications. Full article

This paper presents a novel high-precision 11-bit single-slope/successive approximation register analog-to-digital converter (SS/SAR ADC) architecture specifically designed for CMOS image sensors (CISs). The proposed design solves critical challenges in conventional ADCs by utilizing only two reference voltages, thereby minimizing voltage mismatch and completely eliminating the need for complex switch arrays. This unique approach reduces the transistor count by 64 per column ADC, significantly enhancing area efficiency and circuit simplicity. Furthermore, a groundbreaking on-chip fine step range calibration technique is introduced to mitigate the impact of parasitic capacitance, ensuring the precise alignment between coarse and fine steps and achieving exceptional linearity. Fabricated using a 0.18-µm CMOS process, the ADC demonstrates superior performance metrics, including a differential nonlinearity (DNL) of −1/+1.86 LSB, an integral nonlinearity (INL) of −2.74/+2.79 LSB, an effective number of bits (ENOB) of 8.3 bits, and a signal-to-noise and distortion ratio (SNDR) of 51.77 dB. Operating at 240 kS/s with a power consumption of 22.16 µW, the ADC achieves an outstanding figure-of-merit (${\mathrm{FOM}}_W$) of 0.291 pJ/step. These results demonstrate the proposed architecture’s potential as a transformative solution for high-speed, energy-efficient CIS applications. Full article

Reconfigurable processor-based acceleration of deep convolutional neural network (DCNN) algorithms has emerged as a widely adopted technique, with particular attention on sparse neural network acceleration as an active research area. However, many computing devices that claim high computational power still struggle to execute neural network algorithms with optimal efficiency, low latency, and minimal power consumption. Consequently, there remains significant potential for further exploration into improving the efficiency, latency, and power consumption of neural network accelerators across diverse computational scenarios. This paper investigates three key techniques for hardware acceleration of sparse neural networks. The main contributions are as follows: (1) Most neural network inference tasks are typically executed on general-purpose computing devices, which often fail to deliver high energy efficiency and are not well-suited for accelerating sparse convolutional models. In this work, we propose a specialized computational circuit for the convolutional operations of sparse neural networks. This circuit is designed to detect and eliminate the computational effort associated with zero values in the sparse convolutional kernels, thereby enhancing energy efficiency. (2) The data access patterns in convolutional neural networks introduce significant pressure on the high-latency off-chip memory access process. Due to issues such as data discontinuity, the data reading unit often fails to fully exploit the available bandwidth during off-chip read and write operations. In this paper, we analyze bandwidth utilization in the context of convolutional accelerator data handling and propose a strategy to improve off-chip access efficiency. Specifically, we leverage a compiler optimization plugin developed for Vitis HLS, which automatically identifies and optimizes on-chip bandwidth utilization. (3) In coefficient-based accelerators, the synchronous operation of individual computational units can significantly hinder efficiency. Previous approaches have achieved asynchronous convolution by designing separate memory units for each computational unit; however, this method consumes a substantial amount of on-chip memory resources. To address this issue, we propose a shared feature map cache design for asynchronous convolution in the accelerators presented in this paper. This design resolves address access conflicts when multiple computational units concurrently access a set of caches by utilizing a hash-based address indexing algorithm. Moreover, the shared cache architecture reduces data redundancy and conserves on-chip resources. Using the optimized accelerator, we successfully executed ResNet50 inference on an Intel Arria 10 1150GX FPGA, achieving a throughput of 497 GOPS, or an equivalent computational power of 1579 GOPS, with a power consumption of only 22 watts. Full article

In this paper, we examine an ultra-compact on-chip balanced filter based on novel hybrid resonators (NHRs) comprising short transmission line sections (STLSs) and series LC blocks using low-temperature co-fired ceramic (LTCC) technology. Based on a rigorous theoretical analysis, the proposed NHR demonstrates the potential for intrinsic ultra-wideband differential-mode (DM) and common-mode (CM) suppression without any additional suppressing structures. Furthermore, the resonance of NHRs was determined by four degrees of freedom, providing flexibility for miniaturization. Theoretical extensions of the Nth-order topology can be easily achieved by the simple coupling schemes that occur exclusively between STLSs. For verification, a balanced filter covering the 5G band n78 with an area of 0.065λ_g × 0.072λ_g was designed using the proposed optimization-based design procedure. An ultra-low insertion loss of 0.8 dB was obtained. The quasi-full CM stopband with a 20 dB rejection level ranged from 0 to 12.9 GHz. And the ultra-wide upper DM stopband with a 20 dB rejection level ranged from 4.4 to 11.5 GHz. Good agreement between the theoretical, simulated, and measured results indicate the validity of the proposed design principle. Full article

We reported on a single-longitudinal-mode operated distributed Bragg reflector laser diode emitting at 1950 nm with an on-chip integrated power amplifier. Second-order Chromium–Bragg gratings are carefully designed and fabricated at the end of the ridge waveguide. Achieving a stable single-mode operation with a large injecting current range of 800 mA from 15 °C to 40 °C. The maximum side-mode suppression ratio (SMSR) is up to 42 dB. To increase the output power, an on-chip integrated master oscillator power amplifier (MOPA) is also introduced. MOPA-DBR lasers with different matching configurations between the gain peak and Bragg wavelength are fabricated, resulting in various amplification consequences. The best device is realized with 40 nm red-shifted between Bragg wavelength and photoluminescence (PL) peak. A power amplification of 5.6 times is achieved with the maximum output power of 45 mW. Thus, we put up the feasibility and key design parameters of on-chip integrated power amplification DBR lasers towards mid-infrared. Full article

The failure of different chips under working conditions is influenced by various stress states such as different voltages, temperatures, stress durations, and stress variations. Therefore, the failure time has a great degree of dispersion, and similar chips may exhibit different failure mechanisms due to variations in their working environments. This paper proposes three system-on-chip reliability failure prediction unit circuits: the time-dependent dielectric breakdown prediction circuit, the negative bias temperature instability prediction circuit, and the hot carrier injection prediction circuit. These circuits are embedded within the main chip, enabling real-time failure prediction and reliability mechanism diagnosis in the same working environment as the main chip. The three reliability failure prediction circuits are compact and energy efficient, allowing for their integration into a system on a chip as IP cores that provide early warning signals before system-on-chip failure. Compared to traditional reliability prediction methods, this approach offers the advantages of accurately identifying failure mechanisms, predicting failure times, and enabling real-time online monitoring. Full article

Lens-free on-chip microscopy (LFOCM) is a powerful computational imaging technology that combines high-throughput capabilities with cost efficiency. However, in LFOCM, the phase recovered by iterative phase retrieval techniques is generally wrapped into the range of −$\pi$ to $\pi$, necessitating phase unwrapping to recover absolute phase distributions. Moreover, this unwrapping process is prone to errors, particularly in areas with large phase gradients or low spatial sampling, due to the absence of reliable initial guesses. To address these challenges, we propose a novel biplane phase retrieval (BPR) method that integrates phase unwrapping results obtained at different propagation distances to achieve accurate absolute phase reconstruction. The effectiveness of BPR is validated through live-cell imaging of HeLa cells, demonstrating improved quantitative phase imaging (QPI) accuracy when compared to conventional off-axis digital holographic microscopy. Furthermore, time-lapse imaging of COS-7 cells in vitro highlights the method’s robustness and capability for long-term quantitative analysis of large cell populations. Full article

Lymphocytes are generally non-adherent. This makes it challenging to fabricate three-dimensional (3D) structures mimicking the three-dimensional lymphoma microenvironment in vivo. This study presents the fabrication of a hemispherical 3D lymphoma model using the on-chip Cell Dome system with a hemispherical cavity (1 mm in diameter and almost 300 µm in height). Both the human brain lymphoma cell line (TK) and human B cell lymphoma cell line (KML-1) proliferated and filled the cavities. Hypoxic regions were observed in the center of the hemispherical structures. CD19 expression did not change in either cell line, while CD20 expression was slightly upregulated in TK cells and downregulated in KML-1 cells cultured in the Cell Dome compared to those cultured in two-dimensional (2D) flasks. In addition, both TK and KML-1 cells in the hemispherical structures exhibited higher resistance to doxorubicin than those in 2D flasks. These results demonstrate the effectiveness of the on-chip Cell Dome for fabricating 3D lymphoma models and provide valuable insights into the study of lymphoma behavior and the development of new drugs for lymphoma treatment. Full article

An approach to measuring chemical concentrations using a slotted micro-ring resonator (sMRR) is proposed which is robust to spectral shifts caused by temperature variations. Two 1-D Convolutional Neural Network architectures, ResNet34 and VGG20, were trained for regression, achieving mean squared errors (MSEs) of 1.1251 $\times {10}^{-4}$ and 1.2195 $\times {10}^{-4}$, respectively. The models predict concentrations of water, ethanol, methanol, and propanol (0–100%) from the transmission spectra of a single-ring sMRR etched in heavily doped silicon, operating in the mid-infrared range (290–310 K). Transfer learning adapted the models for datasets with different temperature ranges, analytes (e.g., butanol), and sMRR designs, achieving comparable accuracy. Variations in accuracy across these datasets are also explored. Full article

Integrated optical amplifiers are the building blocks of on-chip photonic systems, and they are often accompanied by a narrowband filter to limit noise. In this sense, a bandwidth-tunable optical amplifier with narrowband filtering function is crucial for on-chip optical circuits and radio frequency systems. The intrinsic loss and coupling coefficients between resonator and waveguide inherently limit the bandwidth. The parity-time symmetric coupled microresonators operating at exceptional points enable near zero bandwidth. In this study, we propose a parity-time symmetric coupled microresonators system operating near EPs to achieve a bandwidth of 46.4 MHz, significantly narrower than bandwidth of 600.0 MHz and 743.2 MHz achieved by two all-pass resonators with identical gain/loss coefficients. This system also functions as an optical bandwidth-tunable filter. The bandwidth tuning ranges from 175.7 MHz to 7.8 MHz as gain coefficient adjusts from 0.2 dB/cm to 0.4 dB/cm. Our scheme presents a unique method to obtain narrow bandwidth from two broadband resonators and serves as an optical bandwidth-tunable filter, thereby paving a new avenue for exploring non-Hermitian light manipulation in all-optical integrated devices. Full article

This study introduces an innovative on-site diagnostic method for rapidly detecting the Streptococcus bovis/Streptococcus equinus complex (SBSEC), crucial for livestock health and food safety. Through a comprehensive genomic analysis of 206 genomes, this study identified genetic markers that improved classification and addressed misclassifications, particularly in genomes labeled S. equinus and S. lutetiensis. These markers were integrated into a portable quantitative polymerase chain reaction (qPCR) that can detect SBSEC species with high sensitivity (down to 10¹ or 10⁰ colony-forming units/mL). The portable system featuring a flat chip and compact equipment allows immediate diagnosis within 30 min. The diagnostic method was validated in field conditions directly from cattle udders, farm environments, and dairy products. Among the 100 samples, 51 tested positive for bacteria associated with mastitis. The performance of this portable qPCR was comparable to laboratory methods, offering a reliable alternative to whole-genome sequencing for early detection in clinical, agricultural, and environmental settings. Full article