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Search Results (3,622)

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8 pages, 797 KiB  
Article
RF Dielectric Permittivity Sensing of Molecular Spin State Switching Using a Tunnel Diode Oscillator
by Ion Soroceanu, Andrei Diaconu, Viorela-Gabriela Ciobanu, Lionel Salmon, Gábor Molnár and Aurelian Rotaru
J. Compos. Sci. 2025, 9(1), 49; https://doi.org/10.3390/jcs9010049 (registering DOI) - 20 Jan 2025
Abstract
We introduce a novel approach to study the dielectric permittivity of spin crossover (SCO) molecular materials using a radio frequency (RF) resonant tunnel diode oscillator (TDO) circuit. By fabricating a parallel plate capacitor using SCO particles embedded into a polymer matrix as an [...] Read more.
We introduce a novel approach to study the dielectric permittivity of spin crossover (SCO) molecular materials using a radio frequency (RF) resonant tunnel diode oscillator (TDO) circuit. By fabricating a parallel plate capacitor using SCO particles embedded into a polymer matrix as an integral part of the inductor (L) capacitor (C) LC tank of the TDO, we were able to extract the temperature dependence of the dielectric permittivity of frequency measurements for a wide selection of resonance values, spanning from 100 kHz up to 50 MHz, with great precision (less than 2 ppm) and in a broad temperature range. By making use of this simple electronic circuit to explore the frequency and temperature-dependent dielectric permittivity of the compound Fe[(Htrz)2(trz)](BF4), we demonstrate the reliability and resolution of the technique and show how the results compare with those obtained using complex instrumentation. Full article
23 pages, 4261 KiB  
Article
Characterisation of Harmonic Resonance Phenomenon of Multi-Parallel PV Inverter Systems: Modelling and Analysis
by Kasun Peiris, Sean Elphick, Jason David and Duane Robinson
Energies 2025, 18(2), 443; https://doi.org/10.3390/en18020443 - 20 Jan 2025
Abstract
Solar PV inverters require output filters to reduce unwanted harmonics in their output, where LCL filters are a more economical choice than larger inductance-only filters. A drawback of these filters is that they can introduce power quality disturbances, especially at higher frequencies (above [...] Read more.
Solar PV inverters require output filters to reduce unwanted harmonics in their output, where LCL filters are a more economical choice than larger inductance-only filters. A drawback of these filters is that they can introduce power quality disturbances, especially at higher frequencies (above 2 kHz). This paper investigates and characterises the resonance phenomenon introduced by different filter types, i.e., LC or LCL, and identifies their behavioural change when combined with multiple parallel grid-tied PV inverter systems. MATLAB/Simulink modelling aspects of PV inverter systems related to resonance phenomenon are presented, including establishing resonance at a specific frequency where potentially large variations in the parameter selection across manufacturers may exist. In addition, a method is developed to establish output filter frequency response through measurements, which is used to develop validated solar PV harmonic models for high-frequency analysis. The low-frequency harmonic models can be used up to the resonant frequency where the current flowing through the filter capacitor is insignificant compared to the current flowing into the electricity network. Full article
(This article belongs to the Special Issue Power Quality and Hosting Capacity in the Microgrids)
17 pages, 9583 KiB  
Article
A CMOS Switched Capacitor Filter Based Potentiometric Readout Circuit for pH Sensing System
by Shanthala Lakshminarayana, Revathy Perumalsamy, Chenyun Pan, Sungyong Jung, Hoon-Ju Chung and Hyusim Park
J. Low Power Electron. Appl. 2025, 15(1), 3; https://doi.org/10.3390/jlpea15010003 - 19 Jan 2025
Viewed by 337
Abstract
This work presents a potentiometric readout circuit for a pH-sensing system in an oral healthcare device. For in vivo applications, noise, area, and power consumption of the readout electronics play critical roles. While CMOS amplifiers are commonly used in readout circuits for these [...] Read more.
This work presents a potentiometric readout circuit for a pH-sensing system in an oral healthcare device. For in vivo applications, noise, area, and power consumption of the readout electronics play critical roles. While CMOS amplifiers are commonly used in readout circuits for these applications, their applicability is limited due to non-deterministic noises such as flicker and thermal noise. To address these challenges, the Correlated Double Sampler (CDS) topology is widely employed as a sampled-data circuit for potentiometric readout, effectively eliminating DC offset and drift, thereby reducing overall noise. Therefore, this work introduces a novel potentiometric readout circuit realized with CDS and a switched-capacitor-based low-pass filter (SC-LPF) to enhance the noise characteristic of overall circuit. The proposed readout circuit is implemented in an integrated circuit using 0.18 µm CMOS process, which occupies an area of 990 µm × 216 µm. To validate the circuit performances, simulations were conducted with a 5 pF load and a 1 MHz input clock. The readout circuit operates with a supply voltage range ±1.65 V and linearly reproduces the pH sensor output of ±1.5 V. Noise measured with a 1 MHz sampling clock shows 0.683 µVrms, with a power consumption of 124.1 µW. Full article
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Figure 1

Figure 1
<p>Implementation of the CDS circuit.</p>
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<p>(<b>a</b>) Implementation of the resistor emulator for input sampling stage; (<b>b</b>) implementation of the resistor emulator for feedback stage.</p>
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<p>Telescopic OPAMP architecture.</p>
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<p>(<b>a</b>) AC response of OPAMP, voltage gain (dB) versus frequency (Hz); (<b>b</b>) DC response of OPAMP, <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>i</mi> <mi>n</mi> </mrow> </msub> </mrow> </semantics></math> (V) versus <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>o</mi> <mi>u</mi> <mi>t</mi> </mrow> </msub> <mo>(</mo> <mi>V</mi> <mo>)</mo> </mrow> </semantics></math>; (<b>c</b>) Noise analysis of OPAMP, noise (µ<math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>r</mi> <mi>m</mi> <mi>s</mi> </mrow> </msub> </mrow> </semantics></math>) versus frequency (Hz).</p>
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<p>Design of CDS circuit with SC-LPF.</p>
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<p>Full chip layout highlighting the proposed CDS with SC-LPF architecture.</p>
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<p>Transient response at the CDS output for input voltage of 1 V with 1 MHz clock and 5 pF load.</p>
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<p>Transient response at the CDS and SC-LPF output for input voltage of 1 V with 1 MHz clock and 5 pF load.</p>
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<p>Output noise performance of CDS and CDS with SC-LPF at pre-layout circuit simulation, noise (<math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>r</mi> <mi>m</mi> <mi>s</mi> </mrow> </msub> </mrow> </semantics></math>) versus frequency (Hz).</p>
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<p>Post extraction simulation of the overall system (<b>a</b>) <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>i</mi> <mi>n</mi> </mrow> </msub> </mrow> </semantics></math> versus <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>o</mi> <mi>u</mi> <mi>t</mi> </mrow> </msub> </mrow> </semantics></math> linearity plot; (<b>b</b>) frequency response.</p>
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32 pages, 8328 KiB  
Article
Magnetic Integrated Multi-Trap Filters Using Mutual Inductance to Mitigate Current Harmonics in Grid-Connected Power Electronics Converters
by Maged Al-Barashi, Aicheng Zou, Yongjun Wang, Wei Luo, Nan Shao, Zeyu Tang and Bing Lu
Energies 2025, 18(2), 423; https://doi.org/10.3390/en18020423 - 19 Jan 2025
Viewed by 207
Abstract
This paper introduces magnetic integrated high-order trap–trap–inductor (TTL) and inductor–trap–trap (LTT) filters featuring two LC-traps designed for grid-tied inverters, aimed at reducing the size of output-power multi-trap filters. The proposed filters exhibit excellent harmonic absorption capabilities alongside a [...] Read more.
This paper introduces magnetic integrated high-order trap–trap–inductor (TTL) and inductor–trap–trap (LTT) filters featuring two LC-traps designed for grid-tied inverters, aimed at reducing the size of output-power multi-trap filters. The proposed filters exhibit excellent harmonic absorption capabilities alongside a compact design. Building on the conventional integrated inductor–capacitor–inductor (LCL) filter, the approach involves connecting a small capacitor in parallel with either the inverter-side or grid-side inductors to create an LC trap. Additionally, a second LC trap can be achieved by integrating the filter capacitor in series with the equivalent trap inductance, established by the magnetic coupling between the grid-side inductor and inverter-side one. This paper thoroughly analyzes the characteristics of the proposed filters. Moreover, a design method is presented to further minimize the size of the output filter components. Finally, validation through simulations and hardware-in-the-loop (HIL) experiments confirms the proposed approach’s effectiveness and feasibility. The integrated designs achieve a size reduction of 35.4% in comparison with the discrete windings. Moreover, these designed filters comply with IEEE standards, maintaining a grid-side current total harmonic distortion (THD) of less than 0.9%, with all current harmonics below 0.3% of the fundamental current. Full article
(This article belongs to the Section F3: Power Electronics)
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Figure 1

Figure 1
<p>H-bridge single-phase grid-connected converter with a (<b>a</b>) <span class="html-italic">TTL</span> filter; (<b>b</b>) <span class="html-italic">LTT</span> filter.</p>
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<p>Circuit configuration of a (<b>a</b>) <span class="html-italic">TTL</span> filter; (<b>b</b>) <span class="html-italic">LTT</span> filter.</p>
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<p>Block diagrams of a (<b>a</b>) <span class="html-italic">TTL</span> filter; (<b>b</b>) <span class="html-italic">LTT</span> filter.</p>
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<p>Bode diagrams of <span class="html-italic">TTL</span>, <span class="html-italic">LTT</span>, and <span class="html-italic">SPRLCL</span> filters.</p>
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<p>Proposed magnetic integration of <span class="html-italic">TTL</span> and <span class="html-italic">LTT</span> filters: (<b>a</b>) integrated inductor core structure of <span class="html-italic">L<sub>i</sub></span> and <span class="html-italic">L<sub>g</sub></span>; (<b>b</b>) simplified magnetic circuit.</p>
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<p>Flowchart of the presented <span class="html-italic">TTL</span> and <span class="html-italic">LTT</span> filters’ design method.</p>
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<p>Dimensions of (<b>a</b>) integrated <span class="html-italic">TTL</span> and <span class="html-italic">LTT</span> windings’ core; (<b>b</b>) discrete <span class="html-italic">SPRLCL</span> windings’ cores.</p>
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<p>Simulink model of the proposed <span class="html-italic">TTL</span> and <span class="html-italic">TTL</span> filter system.</p>
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<p>Simulation results of the proposed <span class="html-italic">TTL</span> filter: (<b>a</b>) waveforms of currents and voltages; (<b>b</b>) grid-side and inverter-side currents’ spectra.</p>
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<p>Simulation results of the proposed <span class="html-italic">LTT</span> filter: (<b>a</b>) waveforms of currents and voltages; (<b>b</b>) grid-side and inverter-side currents’ spectra.</p>
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<p>Simulation results of the discrete <span class="html-italic">SPRLCL</span> filter: (<b>a</b>) waveforms of currents and voltages; (<b>b</b>) grid-side and inverter-side currents’ spectra.</p>
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<p>Simulation dynamic waveforms with a 10 Ω load step-down using the proposed integrated <span class="html-italic">TTL</span> filter.</p>
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<p>Simulation dynamic waveforms with a 10 Ω load step-down using the proposed integrated <span class="html-italic">LTT</span> filter.</p>
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<p>Transient simulation waveforms with a 40 V step-up in the DC-link voltage using the integrated <span class="html-italic">TTL</span> filter.</p>
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<p>Transient simulation waveforms with a 40 V step-up in the DC-link voltage using the integrated <span class="html-italic">LTT</span> filter.</p>
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<p>Diagram of HIL experiment platform.</p>
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<p>Setting of HIL experiments.</p>
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<p>Experimental waveforms and grid-side current spectrum for the integrated <span class="html-italic">LTT</span> filter.</p>
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<p>Experimental waveforms and grid-side current spectrum for the discrete <span class="html-italic">SPRLCL</span> filter.</p>
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<p>Experimental dynamic waveforms with a 10 Ω load step-down using the integrated <span class="html-italic">LTT</span> filter.</p>
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<p>Experimental transient waveforms with a 40 V step-up in DC-link voltage using the integrated <span class="html-italic">LTT</span> filter.</p>
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22 pages, 9371 KiB  
Article
Single-Phase Transformerless Three-Level PV Inverter in CHB Configuration
by Wojciech Kołodziejski, Jacek Jasielski, Witold Machowski, Juliusz Godek and Grzegorz Szerszeń
Electronics 2025, 14(2), 364; https://doi.org/10.3390/electronics14020364 - 17 Jan 2025
Viewed by 369
Abstract
The paper proposes an original single-phase transformerless three-level (S-PT) photovoltaic (PV) inverter in the cascade H bridge (CHB) configuration. The DC-link voltage of the inverter is created by two serial voltage sources with a voltage twice as low as the DC-link voltage. An [...] Read more.
The paper proposes an original single-phase transformerless three-level (S-PT) photovoltaic (PV) inverter in the cascade H bridge (CHB) configuration. The DC-link voltage of the inverter is created by two serial voltage sources with a voltage twice as low as the DC-link voltage. An appropriate VCC DC-link voltage is generated by a two-phase DC-DC boost converter, fed from the string panel output at a level determined by the maximum power point tracking (MPPT) algorithm. Two symmetrical sources with VCC/2 are formed by a divider of two series-connected capacitors of large and the same capacitance. The common mode (CM) voltage of the proposed inverter is constant, and the voltage stresses across all switches, diodes and gate drive circuits are half of the DC-link voltage. The principles of operation of the S-PT inverter, an implementation of a complete gate control system with galvanic isolation for all IGBTs, are also presented. The proposed inverter topologies have been implemented using high-speed IGBTs and simulated in PSPICE, as well as being experimentally validated. Full article
(This article belongs to the Section Power Electronics)
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Figure 1

Figure 1
<p>The S-PT inverter in CHB configuration: (<b>a</b>). Circuit diagram, (<b>b</b>). Generation of two half-supply voltages, (<b>d</b>). The principle of operation of the PWM modulator controlling the DC-DC two-phase boost converter (<span class="html-italic">V<sub>CC</sub></span> = 380 V), (<b>c</b>,<b>e</b>). Block diagrams of the IGBT control system.</p>
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<p>(<b>a</b>). Block diagram of the extended PSCPWM modulator, (<b>b</b>). Time-domain waveforms of the generated gate signals, and the output voltage and current waveforms of the inverter.</p>
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<p>A combined gate drive circuit with galvanic isolation: (<b>a</b>). System block diagram for two channels. (<b>b</b>). General block diagram with input and output voltages and signals.</p>
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<p>The general configuration of the control system based on the STM32L476xx microcontroller.</p>
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<p>P&amp;O MPPT algorithm flowchart.</p>
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<p>Measurement of the grid voltage frequency <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>f</mi> </mrow> <mrow> <mi>g</mi> </mrow> </msub> <mfenced open="[" close="]" separators="|"> <mrow> <mi>n</mi> </mrow> </mfenced> </mrow> </semantics></math> and the phase angle <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>φ</mi> </mrow> <mrow> <mi>i</mi> </mrow> </msub> <mo>(</mo> <mi>n</mi> <mo>)</mo> </mrow> </semantics></math> between the grid voltage and load current vectors.</p>
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<p>The phase angle between the grid voltage and load current.</p>
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<p>The block diagram of the detection and synchronization unit.</p>
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<p>Characteristics of input and output power and efficiency versus the load resistance of the DC-DC boost converter, simulated in PSPICE: (<b>a</b>). Single-phase (<b>b</b>). Two-phase.</p>
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<p>The assembled two-phase DC-DC boost converter with PCBs on test bench.</p>
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<p>Oscillograms of the PWM control signals on the T<sub>9</sub> and T<sub>10</sub> gates (<b>a</b>), and voltages on the collectors of these transistors and the DC voltage at the converter output (<b>b</b>).</p>
Full article ">Figure 12
<p>Output voltages and currents of the S-PT inverter (<b>a</b>) and zoomed view of these voltages and currents (<b>b</b>) simulated in PSPICE. From top to bottom: <span class="html-italic">V<sub>AN</sub></span>; <span class="html-italic">V<sub>BN</sub></span>—complementary half output voltages at points A and B of the inverter, <span class="html-italic">V<sub>DM</sub></span>; <span class="html-italic">V<sub>CM</sub></span>—DMV and CMV differential and common voltages; voltage on the <span class="html-italic">C<sub>PVg</sub></span> capacitance; <span class="html-italic">i<sub>L</sub></span>—inductance current; <span class="html-italic">i<sub>Co</sub></span>—current of the filter capacitor; <span class="html-italic">i<sub>O</sub>—</span>load current, <span class="html-italic">i<sub>Cleak</sub></span>—leakage current of <span class="html-italic">C<sub>PVg</sub></span>; RMS of <span class="html-italic">i<sub>Cleak</sub></span>.</p>
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<p>Resonant path during freewheeling state.</p>
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<p>The energy efficiency (<b>a</b>) and THD characteristics (<b>b</b>) of the S-PT inverter in three-level CHB configuration: <span class="html-italic">I<sub>Om</sub></span>—load current amplitude; <span class="html-italic">I<sub>ORMS</sub></span>—RMS of load current; <span class="html-italic">I<sub>PV</sub>*</span>—output current of the DC-DC two-phase boost converter.</p>
Full article ">Figure 15
<p>Simulated time waveforms of the IGBT collector currents, <span class="html-italic">I<sub>CT</sub></span><sub>1</sub>, <span class="html-italic">I<sub>CT2</sub></span>, <span class="html-italic">I<sub>CT</sub></span><sub>3</sub>, when switching a load current in the selected switching periods.</p>
Full article ">Figure 16
<p>The photograph of the assembled S-PT inverter in three-level CHB configuration.</p>
Full article ">Figure 17
<p>Oscillograms of the generated control signals in two periods of the grid voltage (<b>a</b>) and their zoomed views in selected small fragments of the positive (<b>b</b>) and negative (<b>c</b>) grid voltage half-period. From top to bottom: <span class="html-italic">PWM<sub>A</sub></span>, <span class="html-italic">PWM<sub>B</sub></span>, <span class="html-italic">S</span><sub>1</sub>, and <span class="html-italic">S</span><sub>2</sub>.</p>
Full article ">Figure 18
<p>Oscillograms of the output signals of the S-PT inverter, <span class="html-italic">V<sub>AN</sub></span>; <span class="html-italic">V<sub>BN</sub></span>—complementary half output voltages at points A and B of the inverter, <span class="html-italic">V<sub>DM</sub></span>; <span class="html-italic">V<sub>CM</sub></span>—DMV and CMV differential and common voltages; <span class="html-italic">I<sub>AO</sub></span>, I<sub>BO</sub>—complementary half output currents at points A and B of the inverter; <span class="html-italic">I<sub>O</sub></span>—differential load current.</p>
Full article ">Figure 19
<p>Oscillograms of the voltages generated at the output of the SPLL with a step-phase excitation at the input of +45° (<b>a</b>) and −45° (<b>b</b>).</p>
Full article ">Figure 20
<p>Oscillograms of the voltages generated at the output of the SPLL with a step frequency excitation from 49 Hz to 50 Hz (<b>a</b>) and from 50 Hz to 51 Hz (<b>b</b>).</p>
Full article ">
21 pages, 4325 KiB  
Article
AI-Driven Signal Processing for SF6 Circuit Breaker Performance Optimization
by Philippe A. V. D. Liz, Giovani B. Vitor, Ricardo T. Lima, Aurélio L. M. Coelho and Eben P. Silveira
Energies 2025, 18(2), 377; https://doi.org/10.3390/en18020377 - 17 Jan 2025
Viewed by 387
Abstract
This work presents an approach based on signal processing and artificial intelligence (AI) to identify the pre-insertion resistor (PIR) and main contact instants during the operation of high-voltage SF6 circuit breakers to help improve the settings of controlled switching and attenuate transients. For [...] Read more.
This work presents an approach based on signal processing and artificial intelligence (AI) to identify the pre-insertion resistor (PIR) and main contact instants during the operation of high-voltage SF6 circuit breakers to help improve the settings of controlled switching and attenuate transients. For this, the current and voltage signals of a real Brazilian substation are used as AI inputs, considering the noise and interferences common in this type of environment. Thus, the proposed modeling considers the signal preprocessing steps for feature extraction, the generation of the dataset for model training, the use of different machine learning techniques to automatically find the desired points, and, finally, the identification of the best moments for controlled switching of the circuit breakers. As a result, the models evaluated obtained good performance in the identification of operation points above 93%, considering precision and accuracy. In addition, valuable statistical notes related to the controlled switching condition are obtained from the circuit breakers evaluated in this research. Full article
(This article belongs to the Special Issue Measurement Systems for Electric Machines and Motor Drives)
Show Figures

Figure 1

Figure 1
<p>Examples of current signals.</p>
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<p>Methodology proposed for the development of this work.</p>
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<p>(<b>a</b>) Signal without noise. (<b>b</b>) Signal with noise. (<b>c</b>) Derivative of the signal without noise. (<b>d</b>) Derivative of the signal with noise.</p>
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<p>Defining the search window for the main contact. (<b>a</b>) The search window was defined from the raw current signal and (<b>b</b>) the signal specifically in this window.</p>
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<p>Some responses of the applied filter bank.</p>
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<p>Current and Voltage signals.</p>
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<p>MLP architecture was developed for this work. It has X input neurons, 100 neurons in the hidden layer, and 2 in its output layer.</p>
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<p>AdaBoost with 500 weak classifiers.</p>
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<p>Model Evaluation.</p>
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<p>AdaBoost Learning Curve.</p>
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<p>MLP Learning Curve.</p>
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<p>Automatically Marked Signals.</p>
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<p>Contact Interval Distribution.</p>
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<p>Inrush over years.</p>
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<p>Inrush and Phases.</p>
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<p>Interval between main contact and current zero-crossing.</p>
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<p>Phases interval between main contact and current zero-crossing.</p>
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<p>Phases Synchronization.</p>
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17 pages, 5815 KiB  
Article
A 250 °C Low-Power, Low-Temperature-Drift Offset Chopper-Stabilized Operational Amplifier with an SC Notch Filter for High-Temperature Applications
by Zhong Yang, Jiaqi Li, Jiangduo Fu, Jiayin Song, Qingsong Cai and Shushan Qiao
Appl. Sci. 2025, 15(2), 849; https://doi.org/10.3390/app15020849 (registering DOI) - 16 Jan 2025
Viewed by 353
Abstract
This paper proposes a three-stage op amp based on the SOI (silicon-on-insulator) process, which achieves a low offset voltage and temperature coefficient across a wide temperature range from −40 °C to 250 °C. It can be used in aerospace, oil and gas exploration, [...] Read more.
This paper proposes a three-stage op amp based on the SOI (silicon-on-insulator) process, which achieves a low offset voltage and temperature coefficient across a wide temperature range from −40 °C to 250 °C. It can be used in aerospace, oil and gas exploration, automotive electronics, nuclear industry, and in other fields where the ability of electronic devices to withstand high-temperature environments is strongly required. By utilizing a SC (Switched Capacitor) notch filter, the op amp achieves low input offset in a power-efficient manner. The circuit features a multi-path nested Miller compensation structure, consisting of a low-speed channel and a high-speed channel, which switch according to the input signal frequency. The input-stage operational amplifier is a fully differential, rail-to-rail design, utilizing tail current control to reduce the impact of common-mode voltage on the transconductance of the input stage. The two-stage operational amplifier uses both cascode and Miller compensation, minimizing the influence of the feedforward signal path and improving the amplifier’s response speed. The prototype op amp is fabricated in a 0.15 µm SOI process and draws 0.3 mA from a 5 V supply. The circuit occupies a chip area of 0.76 mm2. The measured open-loop gain exceeds 140 dB, with a 3 dB bandwidth greater than 100 kHz. The amplifier demonstrates stable performance across a wide temperature range from −40 °C to 250 °C, and exhibits an excellent input offset of approximately 20 µV at room temperature and an offset voltage temperature coefficient of 0.7 uV/°C in the full temperature range. Full article
(This article belongs to the Special Issue Advanced Research on Integrated Circuits and Systems)
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Figure 1

Figure 1
<p>Temperature ranges for different electronics applications.</p>
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<p>The structure of the chopper amplifier.</p>
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<p>Chopper amplifier with SC notch filter.</p>
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<p>Auto-zeroing diagram.</p>
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<p>Noise spectrum before and after auto-zeroing.</p>
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<p>Overall circuit structure composition.</p>
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<p>Input-stage operational amplifier circuit.</p>
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<p>The notch filter circuit.</p>
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<p>The spectrum of the notch filter.</p>
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<p>Post-stage operational amplifier circuit.</p>
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<p>The chip micrograph.</p>
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<p>Measurement setup.</p>
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<p>Open-loop gain (with a 100 pF load capacitor at 250 °C).</p>
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<p>Pulse response (with a 5 V step input signal with a cycle time of 10 ms).</p>
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<p>Measurement results versus temperature: (<b>a</b>) gain; (<b>b</b>) GBW; (<b>c</b>) power; (<b>d</b>) offset.</p>
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20 pages, 4910 KiB  
Article
Grid Connection of a Squirrel-Cage Induction Generator Excited by a Partial Power Converter
by Dominik A. Górski, Grzegorz Dziechciaruk and Grzegorz Iwański
Energies 2025, 18(2), 368; https://doi.org/10.3390/en18020368 - 16 Jan 2025
Viewed by 312
Abstract
This article concerns the connection process of a squirrel-cage induction generator to the grid/microgrid. Typically, the generator is unexcited, and its connection to the grid is made directly via a switch. This connection causes a high inrush current and grid voltage drop, which [...] Read more.
This article concerns the connection process of a squirrel-cage induction generator to the grid/microgrid. Typically, the generator is unexcited, and its connection to the grid is made directly via a switch. This connection causes a high inrush current and grid voltage drop, which local consumers notice. This article proposes a robust power system consisting of the squirrel-cage induction generator, a power electronic converter, and a capacitor bank, all connected in parallel. The proposed configuration and a dedicated control system eliminate the inrush current and compensate for the generator’s reactive power during grid-tied operation. The converter controls the generator voltage build-up to adjust the generator voltage to the grid voltage (controlled excitation) and connects the generator to the grid, minimising distortions. Moreover, the system is robust because the failure of the converter does not stop the power generation, unlike a system with a back-to-back converter, where the converter links the generator and the grid. Furthermore, the parallel-connected converter has a significantly reduced power rating because it is only rated for a part of the reactive generator power. The rest of the reactive generator power is delivered by the fixed capacitor bank. The article presents the system configuration, the control method, and laboratory results confirming the system’s effectiveness in maintaining high-quality grid voltage during generator-to-grid connection and high-quality power supplied to the grid. Full article
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Figure 1
<p>The power system configurations equipped with a squirrel-cage induction generator and a power electronic converter: (<b>a</b>) system with a back-to-back converter; (<b>b</b>) system with a parallel connected full reactive power converter; (<b>c</b>) system with a parallel connected partial reactive power converter.</p>
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<p>Universal algorithm for the grid connection of an excited squirrel-cage induction generator (SCIG): (<b>a</b>) system block schematic for the method of synchronising the generator voltage with the grid voltage by loading the induction generator; (<b>b</b>) system block diagram for the asynchronous connection method, where the generator and grid voltage vectors match, but the frequencies are different; (<b>c</b>) general algorithm of the generator-to-grid connection.</p>
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<p>Electrical diagram of small-scale power system used in laboratory setup.</p>
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<p>Laboratory setup of the squirrel-cage induction generator and parallel NPC converter.</p>
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<p>Power electronic converter (PEC) and controlled-load (CL) topologies applied in the analysed system.</p>
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<p>Control system of a power electronic converter applied for generator excitation and grid connection of induction generator: (<b>a</b>) main control circuit, where PEC—power electronic converter, CL—controlled load, CB—capacitor bank; (<b>b</b>) multifunctional subsystem including the reference frame orientation and voltage synchronisation; (<b>c</b>) blocks of Synchronous Reference Frame Phase-Locked Loops (SRF-PLLs) with auxiliary signal outputs.</p>
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<p>The dependency of the reactive generator power as a function of its active power. Additionally, the figure presents the rated power lines of the full and partial power converters at 220 V and 50 Hz.</p>
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<p>Magnetisation curve of an induction generator (<b>a</b>) at 50 Hz with the capacitor bank voltage line for 70 µF and 105 µF and (<b>b</b>) at different frequencies with the capacitor bank voltage lines for 70 µF.</p>
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<p>Currents and voltages for direct grid connection of a squirrel-cage induction generator at a speed equal to 1600 rpm in a laboratory small scale setup—case 1 [<a href="#B13-energies-18-00368" class="html-bibr">13</a>].</p>
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<p>Laboratory test results for generator-to-grid connection using the converter loading method: (<b>a</b>) grid and converter currents for full power converter—case 2 [<a href="#B14-energies-18-00368" class="html-bibr">14</a>]; (<b>b</b>) grid and converter currents for reduced power of converter—case 3.</p>
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<p>Laboratory test results for the converter-controlled excitation of the induction generator at a speed equal to 1600 rpm: generator voltages and converter currents for reduced power converter.</p>
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<p>Laboratory test results for asynchronous generator-to-grid connection method at generator speed equal to 1600 rpm: (<b>a</b>) generator voltages and converter currents for full power converter—case 4 [<a href="#B13-energies-18-00368" class="html-bibr">13</a>]; (<b>b</b>) generator voltages and converter currents for half power converter—case 5.</p>
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23 pages, 5323 KiB  
Article
Entropies in Electric Circuits
by Angel Cuadras, Victoria J. Ovejas and Herminio Martínez-García
Entropy 2025, 27(1), 73; https://doi.org/10.3390/e27010073 - 15 Jan 2025
Viewed by 260
Abstract
The present study examines the relationship between thermal and configurational entropy in two resistors in parallel and in series. The objective is to introduce entropy in electric circuit analysis by considering the impact of system geometry on energy conversion in the circuit. Thermal [...] Read more.
The present study examines the relationship between thermal and configurational entropy in two resistors in parallel and in series. The objective is to introduce entropy in electric circuit analysis by considering the impact of system geometry on energy conversion in the circuit. Thermal entropy is derived from thermodynamics, whereas configurational entropy is derived from network modelling. It is observed that the relationship between thermal entropy and configurational entropy varies depending on the configuration of the resistors. In parallel resistors, thermal entropy decreases with configurational entropy, while in series resistors, the opposite is true. The implications of the maximum power transfer theorem and constructal law are discussed. The entropy generation for resistors at different temperatures was evaluated, and it was found that the consideration of resistor configurational entropy change was necessary for consistency. Furthermore, for the sake of generalization, a similar behaviour was observed in time-dependent circuits, either for resistor–capacitor circuits or circuits involving degradation. Full article
(This article belongs to the Section Multidisciplinary Applications)
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Figure 1
<p>Current divider with two resistors in parallel. <span class="html-italic">E</span> describes a power source, either of voltage or current.</p>
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<p>Voltage divider with two resistors in series. <span class="html-italic">E</span> stands either for a voltage or current source.</p>
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<p>Equivalent series resistance and capacitor with a power source <span class="html-italic">E</span>.</p>
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<p>Configurational entropy (left) and thermal entropy (right) as a function of the normalized resistor ratio for a current source of 1 A and integration time of 1 s. <span class="html-italic">S</span><sub>config</sub> maximum is 0.68 for equal resistors and evolve to 0 when the difference between resistors increases. <span class="html-italic">S</span><sub>therm</sub> increases with <span class="html-italic">R</span><sub>2</sub>.</p>
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<p>Thermodynamic entropy vs. Configurational entropy from a normalized current source (1 A, in black) and normalized voltage source (1 V, in dashed red line) and integrated for 1 s.</p>
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<p>Current through <span class="html-italic">R</span><sub>2</sub> for reference case at constant temperature (black), temperature-dependent resistor with <span class="html-italic">α</span> = 0.0040 (red), temperature-dependent resistor with <span class="html-italic">α</span> = −0.0005 (green), and temperature-independent resistors (blue). All cases considered <span class="html-italic">T</span><sub>1</sub> = 300 K and <span class="html-italic">T</span><sub>2</sub> = 400 K. The difference between the blue curve and the reference curve indicates that it is not possible to modify the thermal dissipation without changing the structure of the material, i.e., the temperature coefficient term proportional to <span class="html-italic">α</span>.</p>
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<p><span class="html-italic">S</span><sub>config</sub> change due to resistance variation on temperature with <span class="html-italic">α</span> = 0.0040 (dashed red line) with respect to the reference configuration (black).</p>
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<p><span class="html-italic">S</span><sub>therm</sub> for reference case (black) and for temperature-dependent resistor with <span class="html-italic">α</span> = 0.0040 (in red) for a current source of 1 A.</p>
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<p><span class="html-italic">S</span><sub>therm</sub> as a function of <span class="html-italic">S</span><sub>config</sub> for reference configuration without temperature variation (black), thermal-dependent resistor with <span class="html-italic">α</span> = 0.0040 (dashed red line) and resistor with <span class="html-italic">α</span> = −0.0005 (dotted blue line) for a current source of 1 A. The difference between curves is related to the configurational entropy change of the resistor due to the heat injection with the consequent temperature variation.</p>
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<p><span class="html-italic">S</span><sub>therm</sub> as a function of <span class="html-italic">S</span><sub>config</sub> for current source (black) and voltage source (dashed red line) for series resistors. The red point of maximum <span class="html-italic">S</span><sub>config</sub> and maximum <span class="html-italic">S</span><sub>therm</sub> corresponds to <span class="html-italic">R</span><sub>1</sub> = <span class="html-italic">R</span><sub>2</sub> as described by the maximum power transfer theorem and pointed out with the arrow.</p>
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<p><span class="html-italic">S</span><sub>therm</sub> as a function of <span class="html-italic">S</span><sub>config</sub> for reference configuration (black) and thermal-dependent resistor (dashed red line) with <span class="html-italic">α</span> = 0.0040 for a voltage source. The difference between both curves is related to the entropy change of the resistor.</p>
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<p>(<b>a</b>) Tree shape network with three elements. (<b>b</b>) <span class="html-italic">S</span><sub>config</sub> for 3 resistor circuit. <span class="html-italic">R</span><sub>1</sub>= 1 Ω, <span class="html-italic">R</span><sub>2</sub> is the variable, <span class="html-italic">R</span><sub>3</sub> is studied for two cases: <span class="html-italic">R</span><sub>3</sub> = 1 Ω (black line), and <span class="html-italic">R</span><sub>3</sub> = 10 Ω (dashed red line). (<b>c</b>) S<sub>therm</sub> for the circuit with <span class="html-italic">R</span><sub>3</sub> = 1 Ω (black line) and <span class="html-italic">R</span><sub>3</sub> = 10 Ω (dashed red line) <span class="html-italic">E</span> = 1 V and (<b>d</b>) S<sub>config</sub> and S<sub>therm</sub> relationship with <span class="html-italic">R</span><sub>3</sub> = 1 Ω (black line) and <span class="html-italic">R</span><sub>3</sub> = 10 Ω (dashed red line), <span class="html-italic">R</span><sub>2</sub> as a variable and <span class="html-italic">E</span> = 1 V. <span class="html-italic">R</span> symmetry is lost when <span class="html-italic">R</span><sub>3</sub> and <span class="html-italic">R</span><sub>1</sub> are different. The arrows point at the maximum <span class="html-italic">S</span><sub>config</sub>.</p>
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<p>(<b>a</b>) Tree shape network with seven elements (<b>b</b>) <span class="html-italic">S</span><sub>config</sub> for 7 resistor circuit. <span class="html-italic">R</span><sub>2</sub> is variable and <span class="html-italic">R</span><sub>3</sub> = 1 Ω (black line) and <span class="html-italic">R</span><sub>3</sub> = 10 Ω (dashed red line). All other resistors are fixed to 1 Ω. (<b>c</b>) <span class="html-italic">S</span><sub>therm</sub> for the circuit with <span class="html-italic">R</span><sub>3</sub> = 1 Ω (black line) and <span class="html-italic">R</span><sub>3</sub> = 10 Ω (dashed red line) <span class="html-italic">E</span> = 1 V and (<b>d</b>) <span class="html-italic">S</span><sub>config</sub> and <span class="html-italic">S</span><sub>therm</sub> relationship with <span class="html-italic">R</span><sub>3</sub> = 1 Ω (black line) and <span class="html-italic">R</span><sub>3</sub> = 10 Ω (dashed red line), <span class="html-italic">R</span><sub>2</sub> as a variable and <span class="html-italic">E</span> = 1 V. Symmetry is lost when <span class="html-italic">R</span><sub>3</sub> and <span class="html-italic">R</span><sub>1</sub> are different.</p>
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<p>(<b>a</b>) Circuit with two voltage sources and two resistors. (<b>b</b>) S<sub>config</sub> − S<sub>therm</sub> relationship for <span class="html-italic">V</span><sub>1</sub> = 1 V, <span class="html-italic">V</span><sub>2</sub> = 2 V and <span class="html-italic">R</span><sub>1</sub> = 1 Ω or 10 Ω. <span class="html-italic">R</span><sub>2</sub> is the swept variable.</p>
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<p>Modulus of S<sub>config</sub> as a function of frequency for <span class="html-italic">C</span> = 1 F, <span class="html-italic">R</span> = 1 Ω (black), and <span class="html-italic">R</span>= 10 Ω (dashed red line).</p>
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<p>Nyquist plot for <span class="html-italic">S</span><sub>config</sub> for <span class="html-italic">R</span> = 1 Ω, <span class="html-italic">C</span> = 1 F, and 1 mHz &lt; <span class="html-italic">ω</span> &lt; 1 kHz.</p>
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<p>Relationship between S<sub>config</sub> and S<sub>therm</sub> for an <span class="html-italic">R-C</span> system (<span class="html-italic">R</span> = 1 Ω, <span class="html-italic">C</span> = 1 F, and <span class="html-italic">T</span> = 300 K). A similar behaviour to resistor circuits is found, showing the generality of the method for linear systems.</p>
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<p>Time dependent profiles for degradation in a parallel <span class="html-italic">R</span><sub>1</sub>//<span class="html-italic">R</span><sub>2</sub> circuit with <span class="html-italic">R</span><sub>1</sub> = 1 Ω, <span class="html-italic">T</span> = 300 K, and <span class="html-italic">I</span> = 1 A. (<b>a</b>) Time evolution of resistor degradation according to Equations (22)–(24). (<b>b</b>) Time dependent evolution of <span class="html-italic">S</span><sub>config</sub>. (<b>c</b>) Time dependent evolution of <span class="html-italic">S</span><sub>therm</sub>. (<b>d</b>) Relationship between <span class="html-italic">S</span><sub>config</sub> − <span class="html-italic">S</span><sub>therm</sub>. (<b>e</b>) Relationship between <span class="html-italic">S</span><sub>config</sub> and <math display="inline"><semantics> <mrow> <mover accent="true"> <mrow> <mi>S</mi> </mrow> <mo>˙</mo> </mover> </mrow> </semantics></math><sub>thermal</sub>.</p>
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<p>Time dependent profiles for degradation in a parallel <span class="html-italic">R</span><sub>1</sub>//<span class="html-italic">R</span><sub>2</sub> circuit with <span class="html-italic">R</span><sub>1</sub> = 1 Ω, <span class="html-italic">T</span> = 300 K, and <span class="html-italic">I</span> = 1 A. (<b>a</b>) Time evolution of resistor degradation according to Equations (22)–(24). (<b>b</b>) Time dependent evolution of <span class="html-italic">S</span><sub>config</sub>. (<b>c</b>) Time dependent evolution of <span class="html-italic">S</span><sub>therm</sub>. (<b>d</b>) Relationship between <span class="html-italic">S</span><sub>config</sub> − <span class="html-italic">S</span><sub>therm</sub>. (<b>e</b>) Relationship between <span class="html-italic">S</span><sub>config</sub> and <math display="inline"><semantics> <mrow> <mover accent="true"> <mrow> <mi>S</mi> </mrow> <mo>˙</mo> </mover> </mrow> </semantics></math><sub>thermal</sub>.</p>
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<p>Relationship between <span class="html-italic">S</span><sub>therm</sub> − <span class="html-italic">S</span><sub>config.</sub> It is the same data from <a href="#entropy-27-00073-f018" class="html-fig">Figure 18</a>d with the axis exchanged.</p>
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25 pages, 15881 KiB  
Article
A Robust Linear Active Disturbance Rejection Control for Renewable Energy Grid-Connected System Based on APF
by Zhenqing Zhao, Kai Song, Boyan Huang, Cong Li, Shulin Jiang, Jiangbo Sun, Hongxu Li and Zihui Lian
Sustainability 2025, 17(2), 632; https://doi.org/10.3390/su17020632 - 15 Jan 2025
Viewed by 377
Abstract
With the energy transition and changes in electrical load structures, harmonic distortion in power systems is increasingly threatening grid stability, especially during the integration of renewable energy sources. Active power filters (APFs) are commonly used to improve power quality, but current fluctuations and [...] Read more.
With the energy transition and changes in electrical load structures, harmonic distortion in power systems is increasingly threatening grid stability, especially during the integration of renewable energy sources. Active power filters (APFs) are commonly used to improve power quality, but current fluctuations and voltage instability caused by DC-side capacitor charging and discharging hinder effective harmonic compensation. To address this, this paper presents a method combining a variable-step-size adaptive linear predictor with linear active disturbance rejection control (VALP-LADRC). By integrating an adaptive linear predictor (ALP) with LADRC, the proposed method effectively reduces the impact of disturbances on control, improving voltage regulation and harmonic compensation, and enhancing renewable energy grid integration. To address delays during the adjustment of initial parameters in the adaptive predictor, we combine it with a variable-step-size algorithm, significantly improving disturbance rejection and tracking accuracy, while solving voltage drop issues. The simulation results in a photovoltaic grid-connected system show that VALP-LADRC effectively mitigates disturbances, ensures voltage stability, and enhances power quality. This approach offers a promising solution for supporting sustainable development through better renewable energy integration and improved power quality. Full article
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Figure 1
<p>Schematic of the first-order LADRC structure.</p>
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<p>Schematic of the ALP-LADRC structure.</p>
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<p>Block diagram of the adaptive linear predictor structure, where <math display="inline"><semantics> <mrow> <mi>x</mi> <mo stretchy="false">(</mo> <mi>n</mi> <mo stretchy="false">)</mo> </mrow> </semantics></math> is the input signal, <math display="inline"><semantics> <mrow> <mi>y</mi> <mo stretchy="false">(</mo> <mi>n</mi> <mo stretchy="false">)</mo> </mrow> </semantics></math> is the output signal, and <math display="inline"><semantics> <mrow> <mi>w</mi> <mo stretchy="false">(</mo> <mi>n</mi> <mo stretchy="false">)</mo> </mrow> </semantics></math> is the filter’s weight.</p>
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<p>Iterative flowchart of the variable-step-size adaptive algorithm.</p>
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<p>Overall block diagram of the simulation system.</p>
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<p>DC-side voltage waveform under normal conditions for four control algorithms.</p>
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<p>Grid current waveforms under four control algorithms in normal conditions: (<b>a</b>) PI; (<b>b</b>) LADRC; (<b>c</b>) ALP-LADRC; (<b>d</b>) VALP-LADRC.</p>
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<p>Grid current THD under four control algorithms in normal conditions: (<b>a</b>) PI; (<b>b</b>) LADRC; (<b>c</b>) ALP-LADRC; (<b>d</b>) VALP-LADRC.</p>
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<p>DC-side voltage waveform under four control algorithms in the case of sudden load change.</p>
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<p>Load current under sudden change.</p>
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<p>Grid current waveform under four control algorithms in the case of load sudden change: (<b>a</b>) PI; (<b>b</b>) LADRC; (<b>c</b>) ALP-LADRC; (<b>d</b>) VALP-LADRC.</p>
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<p>Grid current THD under four control algorithms in the case of sudden load change: (<b>a</b>) PI; (<b>b</b>) LADRC; (<b>c</b>) ALP-LADRC; (<b>d</b>) VALP-LADRC.</p>
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<p>Grid current THD under four control algorithms in the case of sudden load change: (<b>a</b>) PI; (<b>b</b>) LADRC; (<b>c</b>) ALP-LADRC; (<b>d</b>) VALP-LADRC.</p>
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<p>Load current under continuous load step changes.</p>
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<p>DC-side voltage waveform under four control algorithms in the case of continuous load step changes.</p>
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<p>Grid current waveform under four control algorithms in the case of continuous load step changes: (<b>a</b>) PI; (<b>b</b>) LADRC; (<b>c</b>) ALP-LADRC; (<b>d</b>) VALP-LADRC.</p>
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<p>Grid current waveform under four control algorithms in the case of continuous load step changes: (<b>a</b>) PI; (<b>b</b>) LADRC; (<b>c</b>) ALP-LADRC; (<b>d</b>) VALP-LADRC.</p>
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<p>Block diagram of the photovoltaic grid-connected system.</p>
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<p>Equivalent circuit diagram of the solar cell.</p>
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<p>Output characteristic curve family of the solar cell under different irradiance levels at the same temperature: (<b>a</b>) I–V; (<b>b</b>) P–V.</p>
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<p>Output characteristic curve family of the solar cell under different temperatures at the same irradiance: (<b>a</b>) I–V; (<b>b</b>) P–V.</p>
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<p>Flowchart of conductance increment method.</p>
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<p>The three-phase load current of the photovoltaic grid-connected system before the APF is applied: (<b>a</b>) Three-phase load current waveform; (<b>b</b>) Load A-phase current THD.</p>
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<p>Output characteristics of the photovoltaic module: (<b>a</b>) Current waveform variation; (<b>b</b>) Voltage waveform variation.</p>
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<p>DC side voltage after photovoltaic grid connection.</p>
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<p>Three-phase current waveforms under photovoltaic grid connection using LADRC: (<b>a</b>) Three-phase current waveform; (<b>b</b>) A-phase current THD.</p>
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<p>Three-phase current waveforms under photovoltaic grid connection using VALP-LADRC: (<b>a</b>) Three-phase current waveform; (<b>b</b>) A-phase current THD.</p>
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14 pages, 3285 KiB  
Article
Design of Interface ASIC with Power-Saving Switches for Capacitive Accelerometers
by Juncheng Cai, Yongbin Cai, Xiangyu Li, Shanshan Wang, Xiaowei Zhang, Xinpeng Di and Pengjun Wang
Micromachines 2025, 16(1), 96; https://doi.org/10.3390/mi16010096 - 15 Jan 2025
Viewed by 353
Abstract
High-precision, low-power MEMS accelerometers are extensively utilized across civilian applications. Closed-loop accelerometers employing switched-capacitor (SC) circuit topologies offer notable advantages, including low power consumption, high signal-to-noise ratio (SNR), and excellent linearity. Addressing the critical demand for high-precision, low-power MEMS accelerometers in modern geophones, [...] Read more.
High-precision, low-power MEMS accelerometers are extensively utilized across civilian applications. Closed-loop accelerometers employing switched-capacitor (SC) circuit topologies offer notable advantages, including low power consumption, high signal-to-noise ratio (SNR), and excellent linearity. Addressing the critical demand for high-precision, low-power MEMS accelerometers in modern geophones, this work focuses on the design and implementation of closed-loop interface ASICs (Application-Specific Integrated Circuits). The proposed interface circuit, based on switched-capacitor modulation technology, incorporates a low-noise charge amplifier, sample-and-hold circuit, integrator, and clock divider circuit. To minimize average power consumption, a switched operational amplifier (op-amp) technique is adopted, which temporarily disconnects idle op-amps from the power supply. Additionally, a class-AB output stage is employed to enhance the dynamic range of the circuit. The design was realized using a standard 0.35 μm CMOS process, culminating in the completion of layout design and small-scale engineering fabrication. The performance of the MEMS accelerometers was evaluated under a 3.3 V power supply, achieving a power consumption of 3.3 mW, an accelerometer noise density below 1 μg/√Hz, a sensitivity of 1.65 V/g, a measurement range of ±1 g, a nonlinearity of 0.15%, a bandwidth of 300 Hz, and a bias stability of approximately 36 μg. These results demonstrate the efficacy of the proposed design in meeting the stringent requirements of high-precision MEMS accelerometer applications. Full article
(This article belongs to the Special Issue MEMS Inertial Device, 2nd Edition)
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Figure 1
<p>Overall circuit structure.</p>
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<p>Switched-op-amp with switched output stage.</p>
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<p>System schematic simulation results. (<b>a</b>) Detection results when the acceleration signal is 1 g. (<b>b</b>) Detection results when the acceleration signal is 100 mg.</p>
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<p>Switched-op-amp topology.</p>
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<p>The transistor circuit in switched-op-amp.</p>
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<p>Simulation result of the whole circuit.</p>
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<p>Chip photos and MEMS accelerometer test board.</p>
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<p>The transient test for micro-accelerometers.</p>
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<p>Frequency response and noise spectrum closed-loop micro-accelerometers.</p>
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<p>The linearity test.</p>
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<p>The bias instability test.</p>
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23 pages, 14773 KiB  
Article
Reduction in DC-Link Capacitor Current by Phase Shifting Method for a Dual Three-Phase Voltage Source Inverters Dual Permanent Magnet Synchronous Motors System
by Deniz Şahin and Bülent Dağ
World Electr. Veh. J. 2025, 16(1), 39; https://doi.org/10.3390/wevj16010039 - 14 Jan 2025
Viewed by 334
Abstract
This paper presents a carrier waves phase shifting method to reduce the dc-link capacitor current for a dual three-phase permanent magnet synchronous motor drive system. Dc-link capacitors absorb the ripple current generated at the input due to the harmonics of the pulse width [...] Read more.
This paper presents a carrier waves phase shifting method to reduce the dc-link capacitor current for a dual three-phase permanent magnet synchronous motor drive system. Dc-link capacitors absorb the ripple current generated at the input due to the harmonics of the pulse width modulation (PWM). The size, cost, reliability, and lifetime of the dc-link capacitor are negatively affected by this ripple current flowing through it. The proposed method is especially appropriate for common dc-link capacitors for a dual inverter system driving two PMSMs. In this paper, the input current of each inverter is analyzed using Double Fourier Analysis, and the harmonic components of the dc-link capacitor current are determined. The carrier wave phase shifting method is proposed to reduce the magnitude of the harmonics and thus reduce the dc-link capacitor current. Furthermore, the optimum angle between the carrier waves for the maximum reduction in the dc-link capacitor current is analyzed and simulated for different scenarios considering the speed and load torque of the PMSMs. The proposed method is verified through experiments and PMSMs are driven by three-phase voltage source inverters (VSIs) modulated with Space Vector Pulse Width Modulation (SVPWM), which is the most common PWM strategy. The proposed method reduces the dc-link capacitor current by 60%, thereby significantly decreasing the required dc-link capacitance, the volume of the drive system, and its cost. Full article
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<p>Schematic diagram of the dual three-phase VSIs dual PMSMs system.</p>
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<p>The harmonic components of the dc-link capacitor current for various modulation indices: (<b>a</b>) pf = 1, (<b>b</b>) pf = 0.966, (<b>c</b>) pf = 0.866, and (<b>d</b>) pf = 0.707.</p>
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<p>The carrier waves (<b>top</b>) and second carrier harmonic components (<b>bottom</b>) for both VSIs.</p>
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<p>Frequency spectrum of dc-link capacitor current for M = 0.6126 and pf = 0.966 in dual VSIs dual PMSMs system: (<b>a</b>) without phase difference; (<b>b</b>) with phase difference.</p>
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<p>Frequency spectrum of the dc-link capacitor current for various modulation indices in dual VSI dual PMSM system: (<b>a</b>) without phase difference; (<b>b</b>) phase difference = π/2 rad.</p>
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<p>Normalized dc-link capacitor current of dual VSIs dual PMSMs for various phase shifting angle; M = 0.6126 for both VSIs.</p>
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<p>The dc-link capacitor current (<b>a</b>) and frequency spectrum of it (<b>b</b>): (red) zero rad phase difference; (blue) π/2 rad phase difference.</p>
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<p>The RMS value of the dc-link capacitor current for varying speeds (<b>a</b>) and varying load torques (<b>b</b>): (blue) zero rad phase difference; (orange) π/2 rad phase difference.</p>
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<p>The dc-link capacitor current (<b>a</b>) and frequency spectrum of it (<b>b</b>): (red) zero rad phase difference; (blue) π/2 rad phase difference.</p>
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<p>The dc-link capacitor current for varying load torques of PMSM-2.</p>
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<p>The dc-link capacitor current (<b>a</b>) and frequency spectrum of it (<b>b</b>): (red) zero rad phase difference; (blue) π/2 rad phase difference.</p>
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<p>The dc-link capacitor current for varying speeds of PMSM-2.</p>
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<p>Block diagram of the experimental setup.</p>
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<p>Experimental setup of the dual VSIs dual PMSMs system.</p>
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<p>The dc-link capacitor current (green), input voltage (purple), and input current (blue) of dual VSIs dual PMSMs system: (<b>a</b>) without phase difference; (<b>b</b>) with phase difference.</p>
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<p>FFT magnitude of the dc-link capacitor current for dual VSIs dual PMSMs system: (<b>a</b>) without phase difference; (<b>b</b>) with phase difference.</p>
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<p>Dc-link capacitor current for varying speeds of PMSM-1 and PMSM-2.</p>
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<p>Dc-link capacitor current for varying load torques of PMSM-2.</p>
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<p>Dc-link capacitor current for varying speed of PMSM-2.</p>
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<p>Temperature of dc-link capacitor.</p>
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43 pages, 1214 KiB  
Article
DynPy—Python Library for Mechanical and Electrical Engineering: An Assessment with Coupled Electro-Mechanical Direct Current Motor Model
by Damian Sierociński, Bogumił Chiliński, Franciszek Gawiński, Amadeusz Radomski and Piotr Przybyłowicz
Energies 2025, 18(2), 332; https://doi.org/10.3390/en18020332 - 13 Jan 2025
Viewed by 502
Abstract
DynPy is an open-source library implemented in Python (version 3.10.12) programming language which aims to provide a versatile set of functionalities for mechanical and electrical engineers. It enables the user to model, solve, simulate, and report analysis of dynamic systems with the use [...] Read more.
DynPy is an open-source library implemented in Python (version 3.10.12) programming language which aims to provide a versatile set of functionalities for mechanical and electrical engineers. It enables the user to model, solve, simulate, and report analysis of dynamic systems with the use of a single environment. The DynPy library comes with a predefined collection of ready-to-use mechanical and electrical systems. A proprietary approach to creating new systems by combining independent elements defined as classes, such as masses, springs, dampers, resistors, capacitors, inductors, and more, allows for the quick creation of new, or the modification of existing systems. In the paper examples for obtaining analytical and numerical solutions of the systems described with ordinary differential equations were presented. The assessment of solver accuracy was conducted utilising a coupled electro-mechanical model of a direct current motor, with MATLAB/Simulink (R2022b) used as a reference tool. The model was solved in DynPy with the hybrid analytical–numerical method and fully analytically, while in MATLAB/Simulink strictly numerical simulations were run. The comparison of the results obtained from both tools not only proved the credibility of the developed library but also showed its superiority in specific conditions. Full article
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<p>Graphical representation of the BatteryCell dynamic model.</p>
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<p>Definition and output of initialised ODESystem component.</p>
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<p>Preview of analytical solution generation.</p>
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<p>Analytical solution with substituted parameter values.</p>
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<p>Analytical solution values calculated for subsequent time stamps.</p>
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<p>Numerical solution obtained by ODESystem with numerised method.</p>
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<p>Numerical solutions for multiple values of analysed parameters obtained by NumericalAnalysisDataFrame.</p>
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<p>Analytical solutions for multiple values of analysed parameters obtained by NumericalAnalysisDataFrame.</p>
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<p>The equivalent circuit diagram of the analysed DC motor system.</p>
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<p>Rotor supply voltage.</p>
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<p>Motor load torque.</p>
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<p>Armature current —simulational results obtained from <span class="html-italic">DynPy</span> library (HAN, fixed step size <math display="inline"><semantics> <mrow> <mn>0.1</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math>).</p>
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<p>Rotor’s angular velocity—simulational results obtained from <span class="html-italic">DynPy</span> library (HAN, fixed step size <math display="inline"><semantics> <mrow> <mn>0.1</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math>).</p>
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<p>Armature current—simulational results obtained from <span class="html-italic">DynPy</span> with fully analytical solution.</p>
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<p>Rotor’s angular velocity—simulational results obtained from <span class="html-italic">DynPy</span> with fully analytical solution.</p>
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<p><span class="html-italic">DynPy</span> —comparison of results for armature current obtained with hybrid analytical–numerical and fully analytical solution.</p>
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<p><span class="html-italic">DynPy</span> —comparison of results for angular velocity of the rotor obtained with hybrid analytical–numerical and fully analytical solution.</p>
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<p>Block diagram representing a DC motor designed in <span class="html-italic">MATLAB/Simulink</span>.</p>
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<p>Armature current—simulation results in <span class="html-italic">MATLAB/Simulink</span> with variable integration step.</p>
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<p>Angular velocity of the rotor—simulation results in <span class="html-italic">MATLAB/Simulink</span> with variable integration step.</p>
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<p>Armature current—simulation results in <span class="html-italic">MATLAB/Simulink</span> with a specified constant integration step of <math display="inline"><semantics> <mrow> <mn>0.1</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math>.</p>
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<p>Angular velocity of the rotor—simulation results in <span class="html-italic">MATLAB/Simulink</span> with a specified constant integration step of <math display="inline"><semantics> <mrow> <mn>0.1</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math>.</p>
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<p>Armature current—simulation results in <span class="html-italic">MATLAB/Simulink</span> with a specified constant integration step of <math display="inline"><semantics> <mrow> <mn>0.01</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math>.</p>
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<p>Angular velocity of the rotor—simulation results in <span class="html-italic">MATLAB/Simulink</span> with a specified constant integration step of <math display="inline"><semantics> <mrow> <mn>0.01</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math>.</p>
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<p>Schematic representation of the analysed RLC circuit.</p>
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<p>Resistance signal.</p>
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<p>Block diagram representing an RLC circuit designed in extitMATLAB/Simulink.</p>
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<p>Comparison of simulations conducted using the <span class="html-italic">DynPy</span> library with a fixed integration step size of <math display="inline"><semantics> <mrow> <mn>0.1</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math> and <span class="html-italic">MATLAB/Simulink</span> with a variable integration step size.</p>
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<p>DC motor - comparison of simulations conducted using the <span class="html-italic">DynPy</span> library with a fixed integration step size of <math display="inline"><semantics> <mrow> <mn>0.1</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math> and <span class="html-italic">MATLAB/Simulink</span> with a fixed integration step size of <math display="inline"><semantics> <mrow> <mn>0.1</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math>.</p>
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<p>Comparison of simulations conducted using the <span class="html-italic">DynPy</span> library with a fixed integration step size of <math display="inline"><semantics> <mrow> <mn>0.1</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math> and <span class="html-italic">MATLAB/Simulink</span> with a fixed integration step size of <math display="inline"><semantics> <mrow> <mn>0.01</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math>.</p>
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<p>RLC circuit - comparison of simulations conducted using the <span class="html-italic">DynPy</span> library with a fixed integration step size of <math display="inline"><semantics> <mrow> <mn>0.1</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math> and <span class="html-italic">MATLAB/Simulink</span> with a fixed integration step size of <math display="inline"><semantics> <mrow> <mn>0.1</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math>.</p>
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<p>Comparison of simulations conducted using the <span class="html-italic">DynPy</span> library with a fixed integration step size of <math display="inline"><semantics> <mrow> <mn>0.01</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math> and <span class="html-italic">MATLAB/Simulink</span> with a fixed integration step size of <math display="inline"><semantics> <mrow> <mn>0.01</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math>.</p>
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<p>Comparison of simulations conducted using the <span class="html-italic">DynPy</span> library with a fixed integration step sizes of <math display="inline"><semantics> <mrow> <mn>0.01</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math> and <math display="inline"><semantics> <mrow> <mn>0.1</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mi mathvariant="normal">s</mi> </semantics></math> compared with <span class="html-italic">MATLAB/Simulink</span> variable integration step size.</p>
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24 pages, 6850 KiB  
Article
Multi-Objective Coordinated Control of Smart Inverters and Legacy Devices
by Temitayo O. Olowu and Olusola Odeyomi
Electronics 2025, 14(2), 297; https://doi.org/10.3390/electronics14020297 - 13 Jan 2025
Viewed by 313
Abstract
This work proposes multi-objective two-stage distribution optimal power flow (D-OPF) to coordinate the use of smart inverters (SIs) and existing voltage control legacy devices. The first stage of multi-objective D-OPF aims to solve a mixed-integer nonlinear programming (MINLP) formulation that minimizes both voltage [...] Read more.
This work proposes multi-objective two-stage distribution optimal power flow (D-OPF) to coordinate the use of smart inverters (SIs) and existing voltage control legacy devices. The first stage of multi-objective D-OPF aims to solve a mixed-integer nonlinear programming (MINLP) formulation that minimizes both voltage variation and active power loss, with SI modes, SI settings, voltage regulator (VR) taps, and capacitor bank (CB) status as control variables. The Pareto Optimal Solutions obtained from the first-stage MINLP are used to determine the optimal active–reactive power dispatch from the SIs by solving a nonlinear programming formulation in the second stage of the proposed D-OPF. This model guarantees that the setpoints for active–reactive power align with the droop characteristics of the SIs, ensuring practicability and the autonomous dispatch of active–reactive power by the SIs according to IEEE 1547-2018. The effectiveness of the proposed method is tested on the IEEE 123 distribution network by contrasting the two proposed D-OPF models, with one prioritizing SIs for voltage control and power loss minimization and the other not prioritizing SIs. The simulation results demonstrate that prioritizing SIs with optimal mode and droop settings can improve voltage control and power loss minimization. The proposed model (with SI prioritization) also reduces the usage of traditional grid control devices and optimizes the dispatch of active–reactive power. The POS also shows that the SI modes, droops, and legacy device settings can be effectively obtained based on the desired objective priority. Full article
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<p>(<b>a</b>) VW curve. (<b>b</b>) VV curve.</p>
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<p>(<b>a</b>) VV (P-/Q-priority) operating region [<a href="#B29-electronics-14-00297" class="html-bibr">29</a>]. (<b>b</b>) CPF mode.</p>
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<p>Without SI priority (D-OPF-1).</p>
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<p>With SI priority (D-OPF-2) for improved voltage deviation minimization.</p>
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<p>With SI Priority (D-OPF-2) for improved power loss minimization.</p>
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<p>IEEE 123 distribution network with ten solar PVs.</p>
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<p>Optimal SI modes and settings using D-OPF-1: (<b>a</b>) min <math display="inline"><semantics> <mrow> <mi>O</mi> <msub> <mi>F</mi> <mn>1</mn> </msub> </mrow> </semantics></math>; (<b>b</b>) min <math display="inline"><semantics> <mrow> <mi>O</mi> <msub> <mi>F</mi> <mn>2</mn> </msub> </mrow> </semantics></math>.</p>
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<p>Optimal SI modes and settings using D-OPF-1: (<b>a</b>) min <math display="inline"><semantics> <mrow> <mi>O</mi> <msub> <mi>F</mi> <mn>1</mn> </msub> </mrow> </semantics></math>; (<b>b</b>) min <math display="inline"><semantics> <mrow> <mi>O</mi> <msub> <mi>F</mi> <mn>2</mn> </msub> </mrow> </semantics></math>.</p>
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<p>Optimal SI modes and settings using D-OPF-2: (<b>a</b>) min <math display="inline"><semantics> <mrow> <mi>O</mi> <msub> <mi>F</mi> <mn>1</mn> </msub> </mrow> </semantics></math>; (<b>b</b>) min <math display="inline"><semantics> <mrow> <mi>O</mi> <msub> <mi>F</mi> <mn>2</mn> </msub> </mrow> </semantics></math>.</p>
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<p>D-OPF-1 Pareto optimal tap positions of VR<sub>1</sub>, VR<sub>2</sub>, VR<sub>3</sub> and VR<sub>4</sub> for (<b>a</b>) min <math display="inline"><semantics> <mrow> <mi>O</mi> <msub> <mi>F</mi> <mn>1</mn> </msub> </mrow> </semantics></math> and (<b>b</b>) min <math display="inline"><semantics> <mrow> <mi>O</mi> <msub> <mi>F</mi> <mn>2</mn> </msub> </mrow> </semantics></math>.</p>
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<p>D-OPF-2 Pareto optimal tap positions of VR<sub>1</sub>, VR<sub>2</sub>, VR<sub>3</sub> and VR<sub>4</sub> for (<b>a</b>) min <math display="inline"><semantics> <mrow> <mi>O</mi> <msub> <mi>F</mi> <mn>1</mn> </msub> </mrow> </semantics></math> and (<b>b</b>) min <math display="inline"><semantics> <mrow> <mi>O</mi> <msub> <mi>F</mi> <mn>2</mn> </msub> </mrow> </semantics></math>.</p>
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<p>Active–reactive power dispatch for D-OPF-1.</p>
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<p>Active–reactive power dispatch for D-OPF-2.</p>
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<p>Active power curtailment for <math display="inline"><semantics> <mrow> <mi>min</mi> <mi>O</mi> <msub> <mi>F</mi> <mn>1</mn> </msub> </mrow> </semantics></math> and <math display="inline"><semantics> <mrow> <mi>min</mi> <mi>O</mi> <msub> <mi>F</mi> <mn>2</mn> </msub> </mrow> </semantics></math> using D-OPF-1.</p>
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<p>Active power curtailment for <math display="inline"><semantics> <mrow> <mi>min</mi> <mi>O</mi> <msub> <mi>F</mi> <mn>1</mn> </msub> </mrow> </semantics></math> and <math display="inline"><semantics> <mrow> <mi>min</mi> <mi>O</mi> <msub> <mi>F</mi> <mn>2</mn> </msub> </mrow> </semantics></math> using D-OPF-2.</p>
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<p>Optimal tap positions for VR<sub>1</sub>, VR<sub>2</sub>, VR<sub>3</sub>, and VR<sub>4</sub> [<a href="#B28-electronics-14-00297" class="html-bibr">28</a>].</p>
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<p>Optimal SI modes and settings [<a href="#B28-electronics-14-00297" class="html-bibr">28</a>].</p>
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14 pages, 5432 KiB  
Article
Development and Validation of a Capacitor–Current Circuit Model for Evaporation-Induced Electricity
by Wenluan Zhang, Runru Tristan Liu and Yumin Huang
Appl. Sci. 2025, 15(2), 664; https://doi.org/10.3390/app15020664 - 11 Jan 2025
Viewed by 358
Abstract
Evaporation-induced electricity is a promising approach for sustainable energy generation which is particularly suited for off-grid and Internet-of-Things (IoT) applications. Despite significant progress, the mechanism of electricity generation remains debated due to complex factors. In this study, we introduce a simplified capacitor–current circuit [...] Read more.
Evaporation-induced electricity is a promising approach for sustainable energy generation which is particularly suited for off-grid and Internet-of-Things (IoT) applications. Despite significant progress, the mechanism of electricity generation remains debated due to complex factors. In this study, we introduce a simplified capacitor–current circuit model to describe the behavior of evaporation-induced electricity. The primary objective of this work is to provide a framework for understanding the transient and steady-state behavior of this phenomenon. We validated this model using experimental data from wood-based nanogenerators with citric acid modified microchannels. The fitting results revealed a steady-state current of approximately 9.832 μA and an initial peak current of 16.168 μA with a time constant of 621.395 s. These findings were explained by a hybrid model incorporating a capacitor and current source components, and subsequent discharge through internal resistance. This simplified model paves the way for better understanding and optimization of evaporation-induced electricity, highlighting potential improvements in device design for enhanced performance. While improving device performance is beyond the scope of this study, the insights gained from this model offer a foundation for future optimization and the enhanced performance of evaporation-induced electricity generation devices. Full article
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<p>Electrical analogy for evaporation-induced electricity. The arrows indicate the flow direction.</p>
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<p>SEM Image of the wood structure. SEM image displaying the aligned microchannels in the beech wood sample with an average channel diameter of approximately 50 μm. This microstructure facilitates efficient water evaporation and ion transport, essential for the device’s performance.</p>
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<p>FTIR spectra of the wood after citric acid treatment. FTIR spectra showing characteristic peaks at 1730 <math display="inline"><semantics> <mrow> <msup> <mrow> <mi mathvariant="normal">c</mi> <mi mathvariant="normal">m</mi> </mrow> <mrow> <mo>−</mo> <mn>1</mn> </mrow> </msup> </mrow> </semantics></math> (–C=O) and 1156 <math display="inline"><semantics> <mrow> <mi mathvariant="normal">c</mi> <msup> <mrow> <mi mathvariant="normal">m</mi> </mrow> <mrow> <mo>−</mo> <mn>1</mn> </mrow> </msup> </mrow> </semantics></math> (–C–O), indicating successful esterification of hydroxyl groups on the wood surface. These modifications enhance the surface charge and hydrophilicity, promoting better ion transport.</p>
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<p>Contact angle measurement. Contact angle measurement showing the hydrophilicity of the CA-treated wood.</p>
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<p>Zeta potential measurement. Zeta potential measurement of the CA-treated wood, showing a negative surface charge of <math display="inline"><semantics> <mrow> <mo>−</mo> <mn>17.1</mn> </mrow> </semantics></math> mV.</p>
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<p>Device setup of the wood-based nanogenerator. (<b>a</b>) Single device setup for testing current output. (<b>b</b>) Multiple devices series connected and (<b>c</b>) parallel connected to showcase the scale-up setup.</p>
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<p>Short-circuit current vs. time (black) with fitting line (red) using the simplified capacitor–current model.</p>
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<p>Time constant vs. capacitance and steady-state current vs. internal resistance. (<b>a</b>) The time constant (<math display="inline"><semantics> <mrow> <mi>τ</mi> </mrow> </semantics></math>) increases with capacitance (<math display="inline"><semantics> <mrow> <mi>C</mi> </mrow> </semantics></math>) for different internal resistance values (<math display="inline"><semantics> <mrow> <msub> <mrow> <mi>R</mi> </mrow> <mrow> <mi mathvariant="normal">i</mi> <mi mathvariant="normal">n</mi> <mi mathvariant="normal">t</mi> </mrow> </msub> </mrow> </semantics></math>). Higher capacitance and internal resistance result in longer time constants, indicating better charge retention. (<b>b</b>) The steady-state current (<math display="inline"><semantics> <mrow> <msub> <mrow> <mi>I</mi> </mrow> <mrow> <mi mathvariant="normal">s</mi> <mi mathvariant="normal">t</mi> <mi mathvariant="normal">e</mi> <mi mathvariant="normal">a</mi> <mi mathvariant="normal">d</mi> <mi mathvariant="normal">y</mi> </mrow> </msub> </mrow> </semantics></math>) decreases with increasing internal resistance (<math display="inline"><semantics> <mrow> <msub> <mrow> <mi>R</mi> </mrow> <mrow> <mi mathvariant="normal">i</mi> <mi mathvariant="normal">n</mi> <mi mathvariant="normal">t</mi> </mrow> </msub> </mrow> </semantics></math>). Lower resistance values lead to higher steady-state currents, demonstrating the importance of minimizing resistance for device performance.</p>
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