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Keywords = DSSoC

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22 pages, 1584 KiB  
Article
Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip
by A. Alper Goksoy, Sahil Hassan, Anish Krishnakumar, Radu Marculescu, Ali Akoglu and Umit Y. Ogras
J. Low Power Electron. Appl. 2023, 13(4), 56; https://doi.org/10.3390/jlpea13040056 - 17 Oct 2023
Cited by 2 | Viewed by 1860
Abstract
Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored to the target domain minimize task execution times and power consumption. Traditional operating system (OS) schedulers can diminish the [...] Read more.
Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored to the target domain minimize task execution times and power consumption. Traditional operating system (OS) schedulers can diminish the potential of DSSoCs, as their execution times can be orders of magnitude larger than the task execution time. To address this problem, we propose a dynamic adaptive scheduling (DAS) framework that combines the advantages of a fast, low-overhead scheduler and a sophisticated, high-performance scheduler with a larger overhead. We present a novel runtime classifier that chooses the better scheduler type as a function of the system workload, leading to improved system performance and energy-delay product (EDP). Experiments with five real-world streaming applications indicate that DAS consistently outperforms fast, low-overhead, and slow, sophisticated schedulers. DAS achieves a 1.29× speedup and a 45% lower EDP than the sophisticated scheduler under low data rates and a 1.28× speedup and a 37% lower EDP than the fast scheduler when the workload complexity increases. Furthermore, we demonstrate that the superior performance of the DAS framework also applies to hardware platforms, with up to a 48% and 52% reduction in the execution time and EDP, respectively. Full article
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Figure 1
<p>An example of the relationship of the (<b>a</b>) execution time and (<b>b</b>) energy-delay product (EDP) between simple low-overhead (lookup table or LUT) and sophisticated high-overhead schedulers.</p> Full article ">Figure 2
<p>Flowchart describing the construction of an Oracle to dynamically choose the best-performing scheduler at runtime.</p> Full article ">Figure 3
<p>ETF scheduling overhead and fitted quadratic curve.</p> Full article ">Figure 4
<p>A comparison of the average execution time (<b>a</b>–<b>c</b>) and energy-delay product (EDP) (<b>d</b>–<b>f</b>) between DAS, the lookup table (LUT), earliest task first (ETF), and ETF-ideal for three different workloads.</p> Full article ">Figure 5
<p>A comparison of the average job slowdown of DAS, LUT, and ETF for twenty-five workloads.</p> Full article ">Figure 6
<p>A comparison of the average execution times of DAS, LUT, ETF, ETF-ideal, and the heuristic approach.</p> Full article ">Figure 7
<p>Decisions made by the DAS framework represented as bar plots and total scheduling energy overheads of LUT, ETF, and DAS as line plots.</p> Full article ">Figure 8
<p>A comparison of the average execution time (<b>a</b>–<b>c</b>) and energy-delay product (EDP) (<b>d</b>–<b>f</b>) of DAS, LUT, and ETF on a hardware platform for three different workloads.</p> Full article ">Figure A1
<p>Possible regions that cover the comparison between DAS and the fast and slow schedulers.</p> Full article ">Figure A2
<p>Experimental results, showing the average execution times for different <math display="inline"><semantics> <mrow> <msub> <mi>p</mi> <mrow> <mi>s</mi> <mi>f</mi> </mrow> </msub> <mo>/</mo> <msub> <mi>p</mi> <mrow> <mi>s</mi> <mi>s</mi> </mrow> </msub> </mrow> </semantics></math> ratios. The results of the fast and slow schedulers are also indicated in the figure by straight lines. The DAS preselection classifier model used in <a href="#sec4-jlpea-13-00056" class="html-sec">Section 4</a> is also indicated by a red star. The shaded region is where the expected trained model results should be.</p> Full article ">Figure A3
<p>The distribution of the number and type of application instances in the 40 workloads used for the evaluation of the DAS framework in the DSSoC simulator.</p> Full article ">Figure A4
<p>The distribution of the number and type of application instances in the 15 workloads used for the evaluation of the DAS framework in the runtime framework.</p> Full article ">
17 pages, 4694 KiB  
Article
Electrolytes with Micelle-Assisted Formation of Directional Ion Transport Channels for Aqueous Rechargeable Batteries with Impressive Performance
by Yanmin Lu, Fengxiang Zhang, Xifeng Lu, Haihui Jiang, Wei Hu, Libin Liu and Ligang Gai
Nanomaterials 2022, 12(11), 1920; https://doi.org/10.3390/nano12111920 - 4 Jun 2022
Cited by 4 | Viewed by 3145
Abstract
Low-cost and ecofriendly electrolytes with suppressed water reactivity and raised ionic conductivity are desirable for aqueous rechargeable batteries because it is a dilemma to decrease the water reactivity and increase the ionic conductivity at the same time. In this paper, Li2SO [...] Read more.
Low-cost and ecofriendly electrolytes with suppressed water reactivity and raised ionic conductivity are desirable for aqueous rechargeable batteries because it is a dilemma to decrease the water reactivity and increase the ionic conductivity at the same time. In this paper, Li2SO4–Na2SO4–sodium dodecyl sulfate (LN-SDS)-based aqueous electrolytes are designed, where: (i) Na+ ions dissociated from SDS increase the charge carrier concentration, (ii) DS−/SO42− anions and Li+/Na+ cations are capable of trapping water molecules through hydrogen bonding and/or hydration, resulting in a lowered melting point, (iii) Li+ ions reduce the Krafft temperature of LN-SDS, (iv) Na+ and SO42− ions increase the low-temperature electrolyte ionic conductivity, and (v) SDS micelle clusters are orderly aggregated to form directional ion transport channels, enabling the formation of quasi-continuous ion flows without (r.t.) and with (≤0 °C) applying voltage. The screened LN-SDS is featured with suppressed water reactivity and high ionic conductivity at temperatures ranging from room temperature to −15 °C. Additionally, NaTi2(PO4)3‖LiMn2O4 batteries operating with LN-SDS manifest impressive electrochemical performance at both room temperature and −15 °C, especially the cycling stability and low-temperature performance. Full article
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Graphical abstract
Full article ">Figure 1
<p>Room-temperature physicochemical properties of LN-SDS-n: (<b>a</b>) LSV plots, inset is the ESW plot with relative standard deviation (RSD) of ca. 1%, (<b>b</b>) Raman spectra, (<b>c</b>) ionic conductivity plot, (<b>d</b>) shear viscosity plots vs. shear rate, (<b>e</b>) plots of elastic modulus and viscous modulus vs. angular frequency, (<b>f</b>) plots of complex dynamic viscosity vs. angular frequency, and (<b>g</b>) <span class="html-italic">ζ</span>-potential plot.</p> Full article ">Figure 2
<p>(<b>a</b>) DSC curves, inset is the melting point plot (RSD &lt; 0.3%). (<b>b</b>) Plot of freezable water concentration vs. n (RSD &lt; 0.3%). (<b>c</b>) Plots of ionic conductivity vs. temperature. (<b>d</b>) Plots of log <span class="html-italic">σ</span> vs. 1000/<span class="html-italic">T</span>, and 21 m LiTFSI is provided for comparison.</p> Full article ">Figure 3
<p>Molecular dynamic simulation results for low-temperature LN-SDS-90 applying a voltage of 2 V nm<sup>−1</sup> at (<b>a</b>) 258.15 K, (<b>b</b>) 263.15 K, (<b>c</b>) 268.15 K, and (<b>d</b>) 273.15 K.</p> Full article ">Figure 4
<p>(<b>a</b>–<b>f</b>) MSD results for LN-SDS-0 and LN-SDS-90 at temperatures of 298.15–258.15 K, without and with applying voltages of 0.5–2 V nm<sup>−1</sup>, and HBNs of water in LN-SDS-0 (<b>g</b>) and LN-SDS-90 (<b>h</b>) at temperatures of 298.15–258.15 K, applying a voltage of 2 V nm<sup>−1</sup>.</p> Full article ">Figure 5
<p>Electrochemical performance of NTP‖LMO operating with LN-SDS-n at room temperature: (<b>a</b>) GCD curves, (<b>b</b>) rate capability, (<b>c</b>) cycling performance at varying C rates, (<b>d</b>) cycling performance at 5 C, (<b>e</b>) cycling performance at 0.2 C, and (<b>f</b>) Ragone plot.</p> Full article ">Figure 6
<p>Electrochemical performance of NTP‖LMO operating with LN-SDS-90 at: (<b>a</b>) 0 °C and (<b>b</b>) −15 °C. Insets in (<b>a</b>) and (<b>b</b>) are the GCD curves of the final five cycles.</p> Full article ">
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