Open AccessArticle

An Optimized H5 Hysteresis Current Control with Clamped Diodes in Transformer-Less Grid-PV Inverter

Sushil Phuyal

Shashwot Shrestha

Swodesh Sharma

Rachana Subedi

Anil Kumar Panjiyar

and

Mukesh Gautam

^2,*

Department of Electrical Engineering, Tribhuvan University, Pulchowk Campus, Lalitpur 44600, Nepal

Electricity Infrastructure & Buildings Division, Pacific Northwest National Laboratory, Richland, WA 99354, USA

Author to whom correspondence should be addressed.

Electricity 2025, 6(1), 1; https://doi.org/10.3390/electricity6010001

Submission received: 7 November 2024 / Revised: 29 December 2024 / Accepted: 5 January 2025 / Published: 7 January 2025

(This article belongs to the Special Issue Planning, Operation and Control of Power Systems with Large Amounts of Variable Renewable Generation)

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Figure 1
Main circuit of HCH5-D2 inverter topology. "> Figure 2
Resonant circuits of the H5 inverter. (a) Resonant circuit in terms of pole voltages. (b) Resonant circuit in terms of DM and CM voltages. "> Figure 3
Resonant circuit of H5 inverter with current sources. "> Figure 4
Resonant circuits of H5 inverter in various voltage and current source configurations. (a) A single voltage and current source. (b) In the form of two voltage sources. "> Figure 5
Simplified resonant circuit of H5 inverter in the form of single common-mode voltage source. "> Figure 6
Different modes of operation of HCH5D2. Mode (1). Positive power transfer. Mode (2). Positive freewheeling. Mode (3). Negative power transfer. Mode (4). Negative freewheeling. "> Figure 7
A control structure diagram for HCH5D2 inverter system, red arrow representing the five gating signals passed to the MOSFETs of the proposed inverter. "> Figure 8
A visual representation of hysteresis band current control. "> Figure 9
Simulation results of the HCH5-D2 topology showing the DC-link voltage and the corresponding switching pattern. The left plot (a) illustrates the stable DC-link voltage, while the right diagram (b) shows the switching pattern for different switches (S1–S5) over time. "> Figure 10
Simulation results of HCH5-D2 topology. Together, the graphs demonstrate the voltage behavior for both common and differential modes in the simulation of the clamped H5 inverter topology, reflecting stability in common mode and regular AC-like switching in differential mode. "> Figure 11
Comparison of simulation results: current. The HCH5-D2 topology shows almost no leakage current, indicating a more efficient and safer design compared to the fluctuating spikes of leakage current in the H4 topology. "> Figure 12
Comparative FFT analysis. "> Figure 13
Simulation results of the HCH5-D2 topology showing the grid voltage and injected grid current. The voltage and current waveforms are sinusoidal, indicating stable operation of the inverter. "> Figure 14
Experimental setup of HCH5D2 inverter topology. ">

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Abstract

With the rise of renewable energy penetration in the grid, photovoltaic (PV) panels are connected to the grid via inverters to supply solar energy. Transformer-less grid-tied PV inverters are gaining popularity because of their improved efficiency, reduced size, and lower costs. However, they can induce a path for leakage currents between the PV and the grid due to the absence of galvanic isolation. This leads to serious electromagnetic interference, loss in efficiency, and safety concerns. The leakage current is primarily influenced by the nature of the common mode voltage (CMV), which is determined by the switching techniques of the inverter. In this paper, a novel inverter topology of Hysteresis Controlled H5 with Two Clamping Diodes (HCH5-D2) is derived. The HCH5-D2 topology helps decouple the AC part (Grid) and DC part (PV) during the freewheeling period to make the CMV constant, thereby reducing the leakage current. Additionally, the extra diodes help reduce voltage spikes generated during the freewheeling period and maintain the CMV at a constant value. Finally, a 2.2 kW grid-connected single-phase HCH5-D2 PV inverter system’s MATLAB simulation is presented, showing better results compared to a traditional H4 inverter.

Keywords:

common mode voltage; electromagnetic interference; HCH5-D2 topology; leakage current; photovoltaics

1. Introduction

Distributive energy resources (DERs), consisting of various energy types such as solar and wind, as well as battery energy storage systems (BESSs), are generally connected to a centralized or islanded power grid. DERs have been widely adopted in both commercial and residential areas [1]. Also, DERs such as solar energy and wind energy are extensively used to complement BESSs, enabling the storage of excess energy during periods of low demand and its utilization during periods of high demand [2].

During periods of sufficient sunlight, grid integrated inverters are used to inject or store solar energy by converting DC power into AC and involve a feedback loop [3]. Line-frequency transformers are mostly used in commercial photovoltaic (PV) inverters to provide galvanic isolation between PV and the grid, but they are often large, heavy, and expensive. Transformer-less inverters (TLIs) are being developed to increase efficiency, reduce size, and lower costs [4,5,6]. TLIs exhibit higher efficiency due to the absence of losses associated with magnetic coupling, including core and copper losses [7]. However, removing the isolation capability of the transformer requires careful consideration to ensure safety and reliability when connecting solar power directly to the grid [8]. Grounding the PV frame to the earth introduces parasitic capacitances between the PV array and the ground [9], which range from 60 nF/kW to 160 nF/kW in normal conditions. This parasitic capacitance forms an LC resonant circuit consisting of a PV array, grid, and converter circuit, allowing unwanted leakage current to flow into the grid, leading to harmonic content, losses, and electromagnetic interference. The German standard VDE0126-1-1 states that leakage currents over 300 mA must trigger a break within 0.3 seconds and send a fault signal [10].

The leakage current in transformer-less grid-tied PV inverters primarily depends on the magnitude and nature of the common mode voltage (CMV), which is determined by the switching pattern of the inverter switches. In conventional inverter topologies, the CMV is not constant, leading to the injection of leakage current into the inverter and the grid. Many inverter topologies have been developed to manage CMV and improve differential-mode voltage (DMV) performance, as CMV is a primary factor in leakage current. In conventional bridge inverter topologies, CMV is not constant, which leads to leakage current injection into the inverter and potentially into the grid [11]. Moreover, bridge topologies using bipolar modulation can still maintain a constant CMV; however, they suffer from high switching losses and have poor differential mode voltage. Conversely, those using unipolar modulation techniques reduce switching losses but fail to maintain a constant CMV [12]. Therefore, using the H4 topology for leakage reduction with proper efficiency is not possible [13].

To address the aforementioned challenges, several topologies have been proposed, including an effective modulation inverter technique in combined PV settings [14]. Decoupling the AC side from the DC side during freewheeling periods is an effective method for weakening CMV. Various TLI topologies, including H5 [15] (DC side decoupling), H6 [16], and HERIC [17] (AC side decoupling), aim to weaken CMV by decoupling the AC side from the DC side during freewheeling periods. While these approaches reduce CMV fluctuations, simple decoupling can lead to oscillations at resonant frequencies, resulting in instability during freewheeling. Clamping circuits have been introduced to address these oscillations and stabilize CMV [18,19]. Likewise, the novel six-switch topology and control strategy in [20] uses an inductor-bypass approach to maintain a stable common-mode voltage, even when filtering inductors are unmatched, thereby eliminating high-frequency ripples in the stray capacitor voltage. Also, the authors in [8] design a seven switch topology with a unipolar sinusoidal pulse width modulation (SPWM) method, effectively reducing leakage current and maintaining constant common-mode voltage.

Moreover, switched capacitor multilevel inverters are widely researched topologies with reduced EMI due to their inductor-less operation [21]. A recent study on the multilevel transformer-less inverter topology also possesses a great level of scope with advantages on reducing the output filter requirement with the rise in differential mode voltage levels [22,23]. Therefore, the main aim for controlling the transformer-less inverter is to suitably mix both modulation techniques, as proposed in this paper, using the topology of Hysteresis Controlled H5 with Two Clamping Diodes (i.e., HCH5-D2).

The HCH5-D2 topology combines both bipolar and unipolar modulation techniques to reduce CMV fluctuations and maintain efficiency. This paper focuses on the multiple aspects of the HCH5-D2 inverter. Firstly, it provides a detailed common-mode resonant circuit modeling using the back-to-back source transformation method (Section 2). Secondly, it discusses the distinct modes of operation of the inverter (Section 3) and introduces dual control techniques to enhance performance (Section 4). Additionally, this paper presents simulation results using MATLAB/Simulink to validate the effectiveness of the proposed topology (Section 5). Lastly, it concludes with key findings of this study (Section 6).

2. Proposed HCH5-D2 Inverter Topology

The proposed HCH5-D2 inverter topology uses an additional power switch, Q5, compared to the traditional H-bridge circuit, as displayed in Figure 1. Q5 is placed on the photovoltaic (PV) side, giving this converter a DC-decoupling type of TLI configuration. Q5 is responsible for isolating and disconnecting the DC or PV side of the circuit from the main grid by turning off when necessary, thus achieving DC decoupling functionality. Additionally, two clamping diodes are added, as shown in Figure 1, whose function is to clamp the CMV to a constant magnitude during the freewheeling period. Therefore, these diodes help to reduce the CMV spikes created during the freewheeling period and maintain it at a constant value [24].

Stray capacitive effects between the photovoltaic (PV) array terminals and electrical ground are represented by the parasitic capacitance

C_{p v}

in Figure 1. These parasitic capacitances demonstrate the distributed impact of capacitive coupling to stray fields. The pole voltages

V_{A N}

and

V_{B N}

at the positive and negative terminals of the PV array are determined by the switching states of the MOSFETs in the converter topology. Specifically, if the upper MOSFETs Q1, Q3, and Q5 are turned on, the pole voltage will be equal to the DC link voltage

V_{D C}

. Conversely, if the lower MOSFETs Q2 and Q4 are conducting, the pole voltages will be zero volts.

Likewise, Figure 1 illustrates the path of the leakage current

I_{c m}

, which flows through both the phase and neutral lines of the inverter and to the grid. The modulation strategy employed in this hysteresis current control inverter topology produces a combination of common mode (CM) and differential mode (DM) characteristics when generating the inverter switching signals. The improved CM characteristics aim to keep the CMV constant, which reduces the leakage current. Better DM characteristics allow the circuit to generate a multilevel DMV or inverter voltage. As shown in Figure 2a, the circuit in Figure 1 can be resolved into its pole voltages

V_{A N}

and

V_{B N}

The average of the pole voltages is known as the CMV. Similarly, the difference between the pole voltages is known as DMV. CMV and DMV can be expressed as

C M V (V_{C M}) = \frac{V_{A N} + V_{B N}}{2}

(1)

D M V (V_{D M}) = V_{A N} - V_{B N}

(2)

Using Equations (1) and (2), the pole voltages

V_{A N}

and

V_{B N}

can be expressed in terms of

V_{C M}

and

V_{D M}

\begin{matrix} V_{A N} = V_{CM} + \frac{V_{D M}}{2} \\ V_{B N} = V_{CM} - \frac{V_{D M}}{2} \end{matrix}

(3)

Likewise, the equivalent circuit is shown in Figure 2a, and it can be re-expressed in terms of CM and DM voltage according to Equation (3) as in Figure 2b. A comprehensive analysis is shown below to examine the behavior of leakage current in a transformer-less inverter [25].

2.1. Conversion of Voltage Sources into Current Sources

The voltage sources which are in series with reactance can be transformed into their respective current sources as displayed in Figure 3. Both current sources are operating at very high switching frequencies in the order of kHz, whereas grid voltage frequency is just 50 Hz. Therefore, for high-frequency analysis, the grid voltage can be neglected.

The two current sources of Figure 3 in parallel connection can be further resolved into a single current source and with a single voltage source as shown in Figure 4a.

2.2. Conversion of Current Source into Voltage Source

The single current source in parallel with the reactance in Figure 4a is transferred back to the voltage source with a series reactance, as shown in Figure 4b.

The two voltage sources can be added to form total CMV,

V_{t C M}

[26]. The final equivalent circuit, to properly describe the nature of CM current, is shown in Figure 5.

V_{t C M} = V_{C M} + \frac{V_{D M}}{2} (\frac{L_{B} - L_{A}}{L_{B} + L_{A}})

(4)

From Equation (4), it can be understood that when the values of filter inductors

L_{A}

and

L_{B}

are equal, in both phase and neutral of the grid side, then

V_{t C M}

will be equal to

V_{C M}

only with no effect of DM voltage.

2.3. Leakage Current and Resonant Frequency

From Figure 5, the expression of the leakage current is expressed as

I_{C M} = \frac{V_{t C M}}{(X_{L A} | | X_{L B}) + X_{C_{P V}}}

(5)

Equation (5) indicates that leakage current depends on the magnitude as well as the nature of CMV. When the CMV is constant (DC) for each mode of operation, it will be a DC quantity with a resonant frequency of zero. Therefore, the whole denominator of Equation (5) becomes infinity, and hence leakage current tends to zero. Hence, it is concluded that the flow and magnitude of leakage current depend on the value and nature (resonating frequency) of CMV.

The equivalent circuit is called an LC resonant circuit due to the formation of two energy storage elements, i.e., equivalent leakage capacitance,

C_{e q P V}

, and equivalent filter inductance,

L_{e q} = L_{A} | | L_{B}

. The LC circuit will oscillate at a resonance frequency given by Equation (6).

F_{r e s o n a n t} = \frac{1}{2 π} \sqrt{\frac{1}{L_{e q v} C_{e q v}}}

(6)

3. Modes of Operation in Proposed HCH5-D2 Inverter

Unlike a standard H5 topology where the CMV at the freewheeling period is uncertain [15], in the proposed HCH5-D2 topology, the two diodes clamp the pole voltages

V_{A N}

and

V_{B N}

\frac{V_{D C}}{2}

. The upper diode clamps the upper pole voltage and the lower diode clamps the lower pole voltage to

\frac{V_{D C}}{2}

during each of the freewheeling modes. The power transfer in the proposed topology is completed by following four modes of operation.

The switching network in Mode 1 allows energy to flow through switches Q1, Q4, and Q5, from the PV to the grid, to obtain an output of

V_{D C}

; the CMV of this mode is equal to

V_{C M}

V_{D C} / 2

. For Mode 2, all the switches, except Q1, are turned off, and current freewheels through Q1 and diode D3, isolating the DC side from the AC side. The clamping circuit sets the pole voltage

V_{B N}

V_{D C} / 2

, which results in zero output voltage, while

V_{C M}

remains

V_{D C} / 2

. In Mode 3, only switches Q2, Q3, and Q5 are on, which transfer energy and generate an output voltage of

- V_{D C}

. Here, the CMV is still at

V_{C M}

V_{D C} / 2

. Finally, in Mode 4, all switches except Q3 are closed, and the current freewheels through Q3 and diode D1, again decoupling the DC and AC sides. The clamping circuit sets

V_{A N}

V_{D C} / 2

, with zero output voltage and the CMV remaining at

V_{D C} / 2

. The four modes are illustrated together in Figure 6.

Based on these four modes, the pole voltages

V_{A N}

and

V_{B N}

along with the CM and DM voltages are depicted in Table 1. It is evident that DM voltage maintains unipolar performance, i.e., three level voltages

+ V_{p v}

, 0, and

- V_{p v}

. Likewise, CM voltage has a constant value in all of the modes. During freewheeling mode, a diode clamps the pole voltages to

V_{p v} / 2

. As a result, CM voltage remains constant, i.e.,

V_{p v} / 2

in all of the modes of operation.

4. Dual Loop Control Strategy for the Proposed HCH5-D2 Inverter

Figure 7 shows the structure for the control strategy that is implemented for HCH5-D2. The system consists of a photovoltaic panel, a boost converter with MPPT system, an HCH5-D2 inverter, and electromagnetic interference (EMI) filters. The voltage control loop and current control loop are included in the control structure, which are explained in the following subsequent sections.

4.1. Outer DC Link Voltage Control Loop

To extract maximum power from the PV panel, the Perturb and Observe (P&O) algorithm [27] is used. The step up boost converter regulates and adjusts the output voltage of the PV panel to match the target voltage, resulting in maximum power production. This loop regulates DC-link voltage at a constant level. Here, the reference voltage value is set as 400 V. By adjusting the reference DC current Id_ref, voltage regulation is achieved. It should be noted that the current Id_ref represents the active component of the reference grid current, which corresponds to the active power available at the DC side.

4.2. Hysteresis Current Control (Inner Grid)

This loop’s main function is to synchronize the inverter with the grid, i.e., to inject active power to the grid and help to maintain the voltage of DC-link at a fixed value. With the Inverse Park transformation, the alpha component of the current corresponding to Id_ref is used as a reference current in order to set the inverter current to a desirable value. This is achieved from the hysteresis band current controller (HBCC) loop [28]. Moreover, to make the injected reactive power zero, the quadrature current component Iq is made zero according to the Inverse Park transformation. HBCC compares I_inv and I_alpha in order to set I_inv to a desirable value. The magnitude of the actual current (I_inv) is controlled by controlling gating signals of the inverter. Figure 8 shows the variation gate signal in order to maintain the actual current within the tolerance level.

5. Results

The proposed HCH5D2 inverter’s simulation is performed in MATLAB R2022b(Simulink) software with parameters as shown in Table 2. The proposed HCH5D2 topology of the inverter was analyzed and compared with the conventional H4 topology. Grid voltage has been obtained to be in phase with grid current, and hence the unity power factor condition is achieved.

5.1. DC-Link Analysis

With the help of the outer DC-link voltage control loop, the simulation model of HCHD-D2 was able to maintain the DC-link voltage at a constant value of 400 V as shown in Figure 9a.

Likewise, the five different switching signals for the inverter switches, S1–S5, obtained by using the Inverse Park transformation of the DC reference current and hysteresis band current control, are shown in Figure 9b. The upper-level MOSFETs S1 and S3 operate at the grid frequency of 50 Hz, while the lower MOSFETs S2 and S4 operate at variable higher frequencies governed by the hysteresis band controller. The additional MOSFET S5 used for DC decoupling operates in combination with the S2 and S4 switches.

5.2. CMV and DMV Analysis

It can be seen from Figure 10a that the CMV profile is basically constant around

V_{D C} / 2

, which is around 200 V. The upper diode D1 and lower diode D2, during the freewheeling period, were able to clamp the common mode voltage at

V_{D C} / 2

and also reduce the number of spikes. Also, the DMV has a unipolar nature as in Figure 10b, which ensures that the switches of the inverter are subjected to less electrical switching stress, which ensures low switching losses.

5.3. Leakage Current Comparison

The leakage current graphs of the conventional H4 inverter and HCH5-D2 inverter are shown in Figure 11a and Figure 11b, respectively. Comparing the maximum spikes of leakage current, which exceeded 0.6 A in the conventional H4 topology in Figure 11a, this magnitude of current violates the German VDE0126–1–1 standard. Moreover, there is also the possibility of triggering inaccurate signals in several protection devices including circuit breakers. However, in the HCH5-D2, the common mode current is effectively suppressed to a permissible limit by a large instant as compared to that in the H4 inverter. From Table 3, it is seen that the leakage current of the HCH5-D2 comes to around 1.35 mA, which is significantly less than the traditional H4 bridge inverter, i.e., 285 mA.

5.4. Total Harmonic Distortion (THD) Analysis

The THD comparison between the proposed HCH5-D2 inverter and the conventional H4 bridge topology is depicted in Figure 12. For the FFT analysis, 40 cycles of grid current with a fundamental frequency of 50 Hz were examined for both inverter topologies. The analysis reveals that the proposed HCH5-D2 inverter significantly reduces the THD from 13.58% to 9.13%. This indicates that the HCH5-D2 topology helps in minimizing harmonic distortions more effectively compared to the H4 topology. The primary reason for this improvement is the better control over the switching events and the effective suppression of leakage currents and harmonics achieved by the proposed design. Moreover, the optimized modulation strategies and advanced filtering techniques incorporated in the HCH5-D2 inverter contribute to its superior harmonic performance, making it more suitable for grid-connected applications.

5.5. Grid Voltage and Current

The waveform of the output current showed the features of a hysteresis band like the gradual rise and decline pattern to ensure that output current follows the reference path. Similarly, the current was also synchronized with the grid voltage apart from the negligible phase lag that occurred. The minor phase difference that occurred is due to the addition of the filter at the end. The impedance of the filter, before connecting to the grid, creates a small phase difference for the flow of negligible reactive power. Neglecting this, the only active power is being injected to the grid side. These simultaneous waveforms are presented in Figure 13a and Figure 13b, respectively.

Figure 14 displays the experimental setup of the proposed HCH5D2 inverter. The setup consists of several key components labeled in the image, including zero crossing detector, boost converter, HCH5-D2 inverter, cooling circuit, current sensor, and filter circuit, showing the experimental working of the HCH5-D2 topology with a focus on how the output waveforms improve after filtering.

6. Conclusions and Future Work

A 2.2kW grid-connected single-phase HCH5-D2 inverter, alongside its control strategies, has been proposed and verified in this paper. The proposed topology successfully maintains a constant CMV, thereby significantly reducing leakage current in comparison to the conventional H4 topology. Additionally, the topology retains the unipolar characteristics of DMV, ensuring reduced switching stress on the inverter switches and minimizing switching losses. The proposed topology also complies with the German VDE0126-1-1 standard. By using only five switches and hysteresis band current control, this topology ensures simplicity and efficiency. Consequently, the HCH5-D2 topology presents a viable solution for transformer-less PV inverters, particularly in single-phase applications.

In future work, the implementation of active disturbance rejection control (ADRC) could be explored as a method to further mitigate leakage current and enhance system stability. ADRC employs an extended state observer to estimate and compensate for disturbances in real time, which can be particularly effective in managing leakage currents treated as disturbances [29]. This control strategy presents a promising area for future research to improve the performance and reliability of transformer-less PV inverters.

Author Contributions

Conceptualization, S.P., S.S. (Shashwot Shrestha), S.S. (Swodesh Sharma) and R.S.; methodology, S.P., S.S. (Shashwot Shrestha), S.S. (Swodesh Sharma) and R.S.; software, S.P., S.S. (Shashwot Shrestha), S.S. (Swodesh Sharma) and R.S.; validation, S.P., S.S. (Shashwot Shrestha), S.S. (Swodesh Sharma) and R.S.; formal analysis, S.P., S.S. (Shashwot Shrestha), S.S. (Swodesh Sharma) and R.S.; investigation, S.P., S.S. (Shashwot Shrestha), S.S. (Swodesh Sharma) and R.S.; resources, S.P., S.S. (Shashwot Shrestha), S.S. (Swodesh Sharma) and R.S.; data curation, S.P., S.S. (Shashwot Shrestha), S.S. (Swodesh Sharma), R.S., A.K.P. and M.G.; writing—original draft preparation, S.P., S.S. (Shashwot Shrestha), S.S. (Swodesh Sharma) and R.S.; writing—review and editing, A.K.P. and M.G.; visualization, S.P., S.S. (Shashwot Shrestha), S.S. (Swodesh Sharma) and R.S.; supervision, A.K.P. and M.G.; project administration, A.K.P. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Informed Consent Statement

Not applicable.

Data Availability Statement

Data are contained within the article.

Conflicts of Interest

The authors declare no conflicts of interest.

Abbreviations

The following abbreviations are used in this manuscript:

BESS	Battery Energy Storage System
CMV	Common Mode Voltage
DERs	Distributive Energy Resources
DMV	Differential Mode Voltage
EMI	Electromagnetic Interference
HBCC	Hysteresis Band Current Control
LC	Leakage Current
PV	Photovoltaics
TLI	Transformer-Less Inverter

References

Awasthi, A.; Karthikeyan, V.; Das, V.; Rajasekar, S.; Singh, A.K. Energy storage systems in solar-wind hybrid renewable systems. In Smart Energy Grid Design for Island Countries: Challenges and Opportunities; Springer: Berlin/Heidelberg, Germany, 2017; pp. 189–222. [Google Scholar]
Phuyal, S.; Shrestha, S.; Sharma, S.; Subedi, R.; Khan, S. Predictive Load Management Using IoT and Data Analytics. In Proceedings of the International Conference on Artificial Intelligence of Things; Springer: Berlin/Heidelberg, Germany, 2023; pp. 153–168. [Google Scholar]
Vakacharla, V.R.; Gnana, K.; Xuewei, P.; Narasimaharaju, B.; Bhukya, M.; Banerjee, A.; Sharma, R.; Rathore, A.K. State-of-the-art power electronics systems for solar-to-grid integration. Sol. Energy 2020, 210, 128–148. [Google Scholar] [CrossRef]
Shayestegan, M. Overview of grid-connected two-stage transformer-less inverter design. J. Mod. Power Syst. Clean Energy 2018, 6, 642–655. [Google Scholar] [CrossRef]
Salem, M.; Richelli, A.; Yahya, K.; Hamidi, M.N.; Ang, T.Z.; Alhamrouni, I. A comprehensive review on multilevel inverters for grid-tied system applications. Energies 2022, 15, 6315. [Google Scholar] [CrossRef]
Khan, M.N.H.; Forouzesh, M.; Siwakoti, Y.P.; Li, L.; Kerekes, T.; Blaabjerg, F. Transformerless Inverter Topologies for Single-Phase Photovoltaic Systems: A Comparative Review. IEEE J. Emerg. Sel. Top. Power Electron. 2020, 8, 805–835. [Google Scholar] [CrossRef]
Xiao, H. Overview of Transformerless Photovoltaic Grid-Connected Inverters. IEEE Trans. Power Electron. 2021, 36, 533–548. [Google Scholar] [CrossRef]
Biswas, M.; Biswas, S.P.; Islam, M.R.; Rahman, M.A.; Muttaqi, K.M.; Muyeen, S.M. A new transformer-less single-phase photovoltaic inverter to improve the performance of grid-connected solar photovoltaic systems. Energies 2022, 15, 8398. [Google Scholar] [CrossRef]
Pourmirasghariyan, M.; Zarei, S.F.; Hamzeh, M. DC-system grounding: Existing strategies, performance analysis, functional characteristics, technical challenges, and selection criteria-a review. Electr. Power Syst. Res. 2022, 206, 107769. [Google Scholar] [CrossRef]
VDE012611; Automatic Disconnection Device Between a Generator and the Public Low Voltage Grid. Kostal Solar Electric GmbH: Freiburg, Germany, 2008.
Calais, M.; Agelidis, V.G.; Meinhardt, M. Multilevel converters for single-phase grid connected photovoltaic systems: An overview. Sol. Energy 1999, 66, 325–335. [Google Scholar] [CrossRef]
Blaacha, J.; Aboutni, R.; Aziz, A. A comparative study between a unipolar and a bipolar PWM used in inverters for photovoltaic systems. In Proceedings of the 2nd International Conference on Electronic Engineering and Renewable Energy Systems: ICEERE 2020, Saidia, Morocco, 13–15 April 2020; Springer: Berlin/Heidelberg, Germany, 2021; pp. 353–360. [Google Scholar]
Xiao, H.; Wang, X. Full-Bridge Transformerless PV Grid-Connected Inverters. In Transformerless Photovoltaic Grid-Connected Inverters; Springer: Singapore, 2021; pp. 35–128. [Google Scholar] [CrossRef]
Sun, J.; Sun, H.; Jiang, J. An improved modulation method for low common-mode current non-isolated series simultaneous power supply dual-input inverters for new energy generation applications. Electr. Eng. 2024, 106, 1–11. [Google Scholar] [CrossRef]
Victor, M.; Greizer, F.; Bremicker, S.; Hübler, U. Method of Converting a Direct Current Voltage from a Source of Direct Current Voltage, More Specifically from a Photovoltaic Source of Direct Current Voltage, into a Alternating Current Voltage. US Patent 7,411,802, 12 August 2008. [Google Scholar]
Ji, B.; Wang, J.; Zhao, J. High-Efficiency Single-Phase Transformerless PV H6 Inverter With Hybrid Modulation Method. IEEE Trans. Ind. Electron. 2013, 60, 2104–2115. [Google Scholar] [CrossRef]
Schmidt, H.; Siedle, C.K.J. Inverter for transforming a DC voltage into an AC current or an AC voltage. 2003. Available online: https://patents.google.com/patent/EP1369985A2/en (accessed on 7 November 2024).
Liao, Z.; Cao, C.; Qiu, D.; Xu, C. Single-Phase Common-Ground-Type Transformerless PV Grid-Connected Inverters. IEEE Access 2019, 7, 63276–63287. [Google Scholar] [CrossRef]
Xiao, H.; Xie, S.; Chen, Y.; Huang, R. An Optimized Transformerless Photovoltaic Grid-Connected Inverter. IEEE Trans. Ind. Electron. 2011, 58, 1887–1895. [Google Scholar] [CrossRef]
Wei, B.; Guo, X.; Guerrero, J.; Savaghebi, M. Leakage Current Suppression with A Novel Six-Switch Photovoltaic Grid-Connected Inverter. In Proceedings of the 2015 IEEE 10th International Symposium on Diagnostics for Electrical Machines, Power Electronics and Drives (SDEMPED), Guarda, Portugal, 1–4 September 2015; IEEE Press: Piscataway, NJ, USA, 2015; pp. 22–26. [Google Scholar] [CrossRef]
Barzegarkhoo, R.; Forouzesh, M.; Lee, S.S.; Blaabjerg, F.; Siwakoti, Y.P. Switched-Capacitor Multilevel Inverters: A Comprehensive Review. IEEE Trans. Power Electron. 2022, 37, 11209–11243. [Google Scholar] [CrossRef]
Grigoletto, F. Multilevel Common-Ground Transformerless Inverter for Photovoltaic Applications. IEEE J. Emerg. Sel. Top. Power Electron. 2020, 9, 831–842. [Google Scholar] [CrossRef]
Guo, X.; He, R.; Jia, X.; Rojas, C.A. Leakage current reduction of transformerless three-phase cascaded multilevel PV inverter. In Proceedings of the 2015 IEEE 24th International Symposium on Industrial Electronics (ISIE), Rio de Janeiro, Brazil, 3–5 June 2015; pp. 1110–1114. [Google Scholar] [CrossRef]
Dhara, S.; Somasekhar, V. A nine-level transformerless boost inverter with leakage current reduction and fractional direct power transfer capability for PV applications. IEEE J. Emerg. Sel. Top. Power Electron. 2021, 10, 7938–7949. [Google Scholar] [CrossRef]
Srivastava, A.; Seshadrinath, J. Common Mode Leakage Current Analysis of 1ϕ Grid-Tied Transformer Less H-Bridge PV Inverter. In Proceedings of the 2021 International Conference on Sustainable Energy and Future Electric Transportation (SEFET), Hyderabad, India, 21–23 January 2021; pp. 1–6. [Google Scholar] [CrossRef]
Estévez-Bén, A.A.; Alvarez-Diazcomas, A.; Macias-Bobadilla, G.; Rodríguez-Reséndiz, J. Leakage current reduction in single-phase grid-connected inverters—A review. Appl. Sci. 2020, 10, 2384. [Google Scholar] [CrossRef]
Lopez, V.; Žindžiūtė, U.; Ziar, H.; Zeman, M.; Isabella, O. Study on the Effect of Irradiance Variability on the Efficiency of the Perturb-and-Observe Maximum Power Point Tracking Algorithm. Energies 2022, 15, 7562. [Google Scholar] [CrossRef]
Bode, G.; Holmes, D. Implementation of three level hysteresis current control for a single phase voltage source inverter. In Proceedings of the 2000 IEEE 31st Annual Power Electronics Specialists Conference. Conference Proceedings (Cat. No. 00CH37018), Galway, Ireland, 23 June 2000; IEEE: Piscataway, NJ, USA, 2000; Volume 1, pp. 33–38. [Google Scholar]
Saleem, M.; Ko, B.S.; Kim, S.H.; Kim, S.i.; Chowdhry, B.S.; Kim, R.Y. Active disturbance rejection control scheme for reducing mutual current and harmonics in multi-parallel grid-connected inverters. Energies 2019, 12, 4363. [Google Scholar] [CrossRef]

Figure 1. Main circuit of HCH5-D2 inverter topology.

Figure 2. Resonant circuits of the H5 inverter. (a) Resonant circuit in terms of pole voltages. (b) Resonant circuit in terms of DM and CM voltages.

Figure 3. Resonant circuit of H5 inverter with current sources.

Figure 4. Resonant circuits of H5 inverter in various voltage and current source configurations. (a) A single voltage and current source. (b) In the form of two voltage sources.

Figure 5. Simplified resonant circuit of H5 inverter in the form of single common-mode voltage source.

Figure 6. Different modes of operation of HCH5D2. Mode (1). Positive power transfer. Mode (2). Positive freewheeling. Mode (3). Negative power transfer. Mode (4). Negative freewheeling.

Figure 7. A control structure diagram for HCH5D2 inverter system, red arrow representing the five gating signals passed to the MOSFETs of the proposed inverter.

Figure 8. A visual representation of hysteresis band current control.

Figure 9. Simulation results of the HCH5-D2 topology showing the DC-link voltage and the corresponding switching pattern. The left plot (a) illustrates the stable DC-link voltage, while the right diagram (b) shows the switching pattern for different switches (S1–S5) over time.

Figure 10. Simulation results of HCH5-D2 topology. Together, the graphs demonstrate the voltage behavior for both common and differential modes in the simulation of the clamped H5 inverter topology, reflecting stability in common mode and regular AC-like switching in differential mode.

Figure 11. Comparison of simulation results: current. The HCH5-D2 topology shows almost no leakage current, indicating a more efficient and safer design compared to the fluctuating spikes of leakage current in the H4 topology.

Figure 12. Comparative FFT analysis.

Figure 13. Simulation results of the HCH5-D2 topology showing the grid voltage and injected grid current. The voltage and current waveforms are sinusoidal, indicating stable operation of the inverter.

Figure 14. Experimental setup of HCH5D2 inverter topology.

Table 1. CMV and DMV in different modes of operation of HCH5-D2 topology.

Modes	$V_{AN}$	$V_{BN}$	$V_{DM}$	$V_{CM}$
Mode 1 (Positive power transfer)	$V_{D C}$	0	$V_{D C}$	$V_{D C} / 2$
Mode 2 (Positive freewheeling)	$V_{D C} / 2$	$V_{D C} / 2$	0	$V_{D C} / 2$
Mode 3 (Negative power transfer)	0	$V_{D C}$	$- V_{D C}$	$V_{D C} / 2$
Mode 4 (Negative freewheeling)	$V_{D C} / 2$	$V_{D C} / 2$	0	$V_{D C} / 2$

Table 2. Circuit parameters used in MATLAB simulation.

Parameters	Symbol	Value
Grid voltage	$v_{g r i d}$	220 Vrms
Input voltage	$V_{D C}$	400 V
Input capacitors	$C_{i n 1}, C_{i n 2}$	1500 μF
Output filter inductors	$L_{1}, L_{2}$	4.06 mH
Equivalent parasitic capacitor	$C_{P V}$	24 nF
MPPT switching frequency	$f_{s w}$	20 kHz
Output power	$P_{o u t}$	2200 W

Table 3. Leakage current comparison.

Topology	Leakage Current (RMS)
H4 with unipolar modulation	285 mA
H5	1.35 mA

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MDPI and ACS Style

Phuyal, S.; Shrestha, S.; Sharma, S.; Subedi, R.; Panjiyar, A.K.; Gautam, M. An Optimized H5 Hysteresis Current Control with Clamped Diodes in Transformer-Less Grid-PV Inverter. Electricity 2025, 6, 1. https://doi.org/10.3390/electricity6010001

AMA Style

Phuyal S, Shrestha S, Sharma S, Subedi R, Panjiyar AK, Gautam M. An Optimized H5 Hysteresis Current Control with Clamped Diodes in Transformer-Less Grid-PV Inverter. Electricity. 2025; 6(1):1. https://doi.org/10.3390/electricity6010001

Chicago/Turabian Style

Phuyal, Sushil, Shashwot Shrestha, Swodesh Sharma, Rachana Subedi, Anil Kumar Panjiyar, and Mukesh Gautam. 2025. "An Optimized H5 Hysteresis Current Control with Clamped Diodes in Transformer-Less Grid-PV Inverter" Electricity 6, no. 1: 1. https://doi.org/10.3390/electricity6010001

APA Style

Phuyal, S., Shrestha, S., Sharma, S., Subedi, R., Panjiyar, A. K., & Gautam, M. (2025). An Optimized H5 Hysteresis Current Control with Clamped Diodes in Transformer-Less Grid-PV Inverter. Electricity, 6(1), 1. https://doi.org/10.3390/electricity6010001

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