1. Introduction
The high-resolution three-dimensional (3-D) time-of-flight (TOF) laser detection and ranging (LADAR) sensors have been developed in various fields such as remote sensing, 3-D imaging, geographical mapping, and range-finding [
1,
2,
3,
4,
5]. A LADAR sensor has difficulty processing all reflected TOF signals for the region of interest (ROI) in every direction when obtaining 3-D imaging information in real-time. To resolve this, many solutions such as the rotational motor (RM)-based method [
6], focal-plane-array (FPA) of the photodetectors-based method [
7], and the static unitary detector (STUD)-based method [
8,
9] have been proposed. As both RM-based and FPA-based methods have a structural limitation to increase 3-D resolution, the STUD-based method has been developed to obtain high spatial resolution 3-D images with many advantages. It has one signal processing chain and does not need micro-lenses to enhance the signal-to-noise ratio (SNR), resulting in cost effectiveness.
In a STUD-based LADAR sensor, as shown in
Figure 1, two high-speed optical scanners (in vertical and horizontal direction) and a large-sized photodetector are conjugated instead of a rotational motor or the FPA of a photodetector. The transmitter illuminates a collimated pulse laser beam in a specific direction over the entire ROI using two high-speed optical scanners with a fixed scanning step size, and the receiver detects returned pulse laser signals using a large-area photodetector. In order to increase 3-D resolution in a STUD-based LADAR sensor, the photosensitive area of a photodetector has to be increased to enlarge the ROI. However, as the increase in the photodetector area decreases its bandwidth due to an increased parasitic capacitance (
CPD), this causes a large timing error (i.e., walk error [
10,
11]). In order to effectively increase the photodetector area with no harm to its bandwidth, the partitioning photosensitive cell (PPC) method has been proposed in earlier studies [
8,
9], as shown in
Figure 2. In order to independently amplify the received signal, each partitioned cell has its own transimpedance amplifier (TIA), and a signal combiner sums the outputs from all TIAs. It has theoretically no limitation in increasing the number of cells, and a high-resolution 3-D image acquisition is possible on a large ROI even with a short laser pulse. However, previous works [
9] focused only on implementing the proposed PPC method embedded in a STUD-based LADAR sensor with a fully integrated four-input-combining receiver, which did not consider the high spatial resolution of 3-D imaging. Although a bandwidth limitation caused by a large C
PD could be solved by applying the PPC method, the unexpected performance degradation could be caused by the pattern of multiple partitioning and signal combining as the number of partitioning photosensitive cells increases.
In this study, we propose a prototype STUD-based LADAR sensor with a large-area photosensitive cell for high spatial resolution 3-D imaging commercial applications. With the fixed scanning step size of the optical scanner, a large ROI with a photosensitive area of approximately 500 μm × 2240 μm corresponding to the CPD of approximately 32 pF is required in a STUD-based LADAR sensor for high spatial resolution commercial applications. Based on the analysis of the PPC method, the effective number of partitioning photosensitive cells and signal-combining stages is selected to read out a large photosensitive cell with optimum performances. A 16-to-1 transimpedance-combining amplifier (TICA) is proposed and fully implemented on a single chip as a front-end readout circuit.
The rest of this paper is organized as follows. The analysis of the PPC method is discussed in
Section 2. The circuit implementation details of the proposed STUD-based LADAR receiver are described in
Section 3. The experimental results of this prototype chip are presented in
Section 4, followed by the conclusion in
Section 5.
2. Analysis of Photodetector Partitioning Cell Method
The block diagram of the proposed STUD-based LADAR receiver embedding the PPC method is illustrated in
Figure 3. The TICA has multiple input current buffers, as many as partitioned photosensitive cells, and the input current buffer is the same as for the conventional TIA. The output signals of each input current buffer are combined into a single output signal (
VPDT) that is amplified using a post-amplifier (
VTICA). The TICA consists of four main blocks: the over-current protection (OCP) circuit, input current buffer, signal combining chain, and post-amplifier. The OCP prevents the fabricated chip from being destructed by a high optical power input signal. The input current buffer acts as a low-impedance input stage to receive optical current. The signal-combining chain sums up the all outputs from the input current buffers. The post-amplifier is designed to maintain the bandwidth and to enhance the transimpedance gain. In order to verify the prototype chip, the output of the post-amplifier is extracted as the output of the TICA from a balun and an output buffer.
In order to implement the PPC method, the effective number of partitioned photosensitive cells (
NIN) and the number of signal-combining stages (
M) have to be considered along with the required performance of the STUD-based LADAR sensor. Note that
NIN is the same as the number of input channels in the TICA as mentioned before. As the single input current buffer of the TICA is the same as for the TIA,
NIN can be determined along with the coverable parasitic capacitance (
CPDS) of the TIA. Once the target
CPDS is set in the first step,
NIN can be defined as follows:
Here,
CPDT is the total parasitic capacitance of the photosensitive cell.
M is the binary-weighted number because
NIN has to be a multiple of twp for the optimum implementation of TICA at the circuit level [
8]. In this work,
CPDS of 2 pF is targeted, so that a 16-to-1 TICA is proposed with
CPDT of 32 pF, resulting in a partitioning number
NIN of 16.
The output signals of 16 input current buffers can be combined in forms of several combining patterns (
NCI) into an output signal of the TICA,
VTICA.
Figure 4 represents the number of signal-combining stages (
M) according to the number of combining input current buffers
NCI. As in conjunction with the formula expressed in equation (1),
NCI is a multiple of two. The number of signal-combining stages
M decreases as the number of combining input current buffers
NCI increases. As each combining stage requires an additional static bias current, decreasing
M is suitable for a low power design. When
NCI is selected as 16, all the output signals of input current buffers combine into the first combining stage in case of '
M = 1’.
The signal summation of the first combining stage occurs at resistor
RL, as shown in Figure 7 (explanation will be followed), defining the transimpedance gain of the first combining stage. Thus, the DC bias current of each input current buffer should be divided by
NCI to properly maintain the DC bias voltages of the first combining stage with a suitable transimpedance gain. As the DC bias voltage of each combining stage is set as the bias voltage of the next combining stage, the DC bias current of each combining stage can be calculated to a specific value.
Figure 5 represents the simulated output peak voltages as functions of the input current and the number of combining input current buffers
NCI. Here, the transimpedance gain is assumed to be approximately 70 dB·Ω. As the number of combining input current buffers
NCI increases, the maximum output peak voltage of the input current buffer is limited by the DC output bias current, resulting in a decrease in the dynamic range. This means that the maximum detectable current of the TICA decreases as the number of combining input current buffers
NCI increases.
Figure 6 represents the power consumption and bandwidth of the TICA according to the number of combining input current buffers
NCI. Here, all simulated results are normalized by the case of ‘
NCI = 2’. As the number of combining input current buffers
NCI increases, the power consumption and bandwidth of the TICA decrease due to the decrease in the static bias current of the combining stage and the DC bias current of the input current buffer, respectively. On the other hand, the power consumption and bandwidth of the TICA increase as the number of combining input current buffers
NCI decreases. In order to get the optimum performances, a proper value of
NCI should be selected when considering the bandwidth and power consumption of the TICA. Considering above all, we choose the number of combining input current buffers
NCI as 4 and the number of signal combining stages
M as 3. In this work, 16 input channels and 3 signal-combining stages TICA topology embedding the PPC method are designed for a large photosensitive cell with
CPDT of 32 pF.
3. Prototype LADAR Receiver Implementation
The required transimpedance gain of the TICA is calculated from its minimum input current. For a lens of diameter 40 mm in the LADAR receiver and a laser peak power of 5 kW in the LADAR transmitter, the calculated returned laser power is approximately 1.5–11.5 μW for a maximum detectable range of 100 m. Here, the returned laser power is calculated using Ref. [
12]. This value corresponds to the minimum input optical current of 9–69 μA when an avalanche photodiode (APD) responsivity is approximately 6 A/W. Thus, a minimum input current of 5 μA is targeted for the proposed TICA in order to have sufficient margin, and then the targeted maximum input-referred rms current noise is calculated as 0.5 μA when the signal-to-noise ratio is 10 [
13,
14]. For signal processing in the LADAR receiver, a timing comparator generating the arrival time of the returned laser signal is used next to the TICA [
7], which is implemented outside the prototype chip in this work. Considering the hysteresis of the timing comparator for noise immunity, the target minimum output voltage of the TICA has to be above 15 mV for a minimum input current of 5 μA. Thus, in this work, the transimpedance gain of the TICA is targeted to be approximately 70 dB·Ω.
As each input channel of the TICA is the same as the TIA, the bandwidth of the TICA converges to that of the TIA. The required bandwidth (BW) of TIA can be calculated from Ref. [
4] as follows:
where
is the rise time of the input optical pulse. In this work, the full width at half maximum (FWHM) of the input pulse is approximately 3.8 ns and its rise time is approximately 1.5 ns. The targeted bandwidth is approximately 230 MHz.
3.1. 16-to-1 Transimpedance Combining Amplifier
Figure 7 illustrates the schematic of the proposed 16-to-1 TICA. It has 16 copies of TIAs as current input buffers, and a TIA has the regulated cascode (RGC) topology based on the inverter local feedback for a low-input impedance [
15]. The small-signal input impedance (
ZIN) of the TIA is approximately given by:
where
and
are the transconductance of transistors
M1 and
M2, respectively. The transimpedance gain of the 16-to-1 TICA for the single signal path can be simplified as follows:
where
ZRGC,
AV,C2, and
AV,C3 are the voltage gains of the first, second, and third combining stages, respectively.
gm5 and
gm9 are the transconductance of transistors
M5 and
M9, respectively.
B is the size ratio of transistors
M6 and
M7.
The −3-dB bandwidth of the TICA is given by:
where
Cin,total is the total input capacitance of the TICA that is given by
Cin,total ≈
CPDS +
Cg2 +
Cs1+
Cs4.
As a noise performance inspection, the proposed TICA with the PPC method has a relatively lower noise bandwidth compared to the wide bandwidth TIA for the large size of CPDT. Although the noise from multiple photosensitive cells is summed up in the signal-combining stage, the SNR is not degraded in the STUD-based LADAR sensor because the returned laser power of the STUD sensor is notably higher than in other LADAR receivers. In the STUD-based LADAR sensor, the transmitter illuminates one collimated pulse laser beam at a time in a specific direction over the entire ROI. On the other hand, in other types of LADARs, the transmitter illuminates over the entire ROI at a time.
3.2. Post Amplifier and Over Current Protection Circuit
The post amplifier is designed using a two-stage common-source amplifier: The first stage has an active inductor load consisting of a transistor
M12 and a resistor
RI to improve its bandwidth [
16], and the second stage is for the pulse polarity and additional voltage gain. A high-input photocurrent generated by a high optical input power increases the input voltage of the TIA beyond the breakdown voltage [
7,
10]. The over-current protection circuit (OCP) is designed in order to protect the 16-to-1 TICA from the damage caused by a high-input photocurrent. The OCP is designed to turn on when the source voltage of
M4 is larger than 1.2 V, and the size ratio of
M3 and
M4 are designed to sufficiently sink by several mA in this work.
3.3. Balun and Output Buffer
Figure 8 shows the schematic of a balun and output buffer. The balun and output buffer are designed in order to verify the outputs of the prototype chip. The balun is designed as a differential amplifier structure biased in the same DC common level, and it converts the single output signals of the TICA into differential output signals. An LPF is inserted into one of the inputs of the balun for DC coupling, whereas the other input receives the output signal of the TICA with its own DC bias. The output buffer is also designed as a differential amplifier structure in order to match the output impedances at both positive and negative output nodes with resistor loads of 50 Ω.
4. Measurement Results
The prototype STUD-based LADAR receiver with a 16-to-1 TICA was fabricated in a 0.18 μm CMOS process. The test board photographs with the prototype chip are shown in
Figure 9. The prototype STUD-based LADAR receiver was implemented in a chip size of 1 mm × 2.5 mm with peripheral circuitry and I/O pads as shown in
Figure 9a. The prototype InGaAs APD was adopted in this design and had a size of 500 μm × 2240 μm with
CPDT of 32 pF. The photosensitive area of the APD was partitioned into 16 cells, and the size of each cell was 500 μm × 140 μm with
CPDS of 2 pF. The two types of measurements, electrical pulse response without the APD (
Figure 9a) and the optical pulse response with the wire-bonded APD (
Figure 9b), were applied in order to verify the prototype chip.
In the electrical pulse response test, an electrical current pulse of width 3 ns and a rising and falling time less than 1.5 ns were concurrently induced in all inputs with the same amplitude at a repetition rate of 10 kHz. The prototype chip was mounted on a wire-bonded chip-on-board (COB) module as shown in
Figure 10a. A resistor 10 kΩ of input node acts as a voltage-to-current converter. To verify the transient response of the prototype receiver, an electrical pulse signal is generated by a pattern generator (Agilent 81110A), and it is applied to each input channel of the implemented test fixture as shown in
Figure 10b. The OUT+ and OUT− signals were measured using a Rohde & Schwarz RTO2024 oscilloscope.
Figure 11 shows the dependence of the 16-to-1 TICA output voltage amplitude as the input current sweep. The measured output voltage swing is linear at the input current sweeps from 3 uA to 73 uA for OUT+, and its maximum output peak voltage is approximately 240 mV. This implies that the transimpedance gain of TICA is approximately 70.4 dB·Ω and it matches well with the targeted transimpedance gain.
The measured output rms noise of the oscilloscope and the prototype chip are shown in
Figure 12a,b, respectively. The output rms noise of the receiver was measured in the electrical pulse response test environment. The output rms noise of a 16-to-1 TICA was measured using the RMS calculation function of the oscilloscope with no input signal source [
17], and the standard deviation of the output of the TICA was measured to be 1.793 mV. After subtracting the inherent oscilloscope noise of 353 μmV
rms, the output noise of the TICA could be estimated as 1.759 mV
rms. The input-referred noise for each input was calculated as approximately 0.64 μmA
rms [
18]. When considering the TIA bandwidth of approximately 230 MHz, the input-referred noise current is calculated as approximately 41.9 pA/√Hz.
In the optical response test, the measurement was carried out using an optical laser pulse of wavelength 1550 nm, FWHM 3.8 ns, rising and falling time 1.5 ns, and a repetition rate of 120 kHz through an attenuator and collimator.
Figure 13 shows the linear dependency of the TICA output (
VTICA) on the optical laser power sweep. As it is difficult to control the optical laser power of the optical laser pulse generator, the optical laser power was increased by the attenuation level control of the attenuator in this work. As the attenuation level increased from 23 dB to 38 dB, the output peak voltage of TICA decreased from 240 mV to 5 mV.
The two-dimensional (2-D) optical scanning test was performed using the test fixture as shown in
Figure 14. The 16 partitioned APD cells and the prototype receiver were mounted on a wire-bonded COB module. The illuminated spot on the APD was changed at a time using the mechanical two stepper motors in two directions (X and Y), and its optical focusing was controlled in Z direction. The output peak voltage of the prototype chip was measured using an oscilloscope.
Figure 15 shows the 2-D scanned intensity images of two prototype chip samples. The 2-D output voltages were collected at a position behind the focal point from a 2500 μm × 2500 μm area with a scan resolution of 50 μm × 50 μm. As the range information could not be obtained in the space between the partitioned cells, the spot size of the focused laser beam had to be set to be larger than the space between the partitioned cells by adjusting the focusing level in Z direction (Z-3000 μm).
However, as the InGaAs APD was implemented as 16 partitioned cells in the prototype chip, the variation of APD is larger than the conventional one inducing the fixed pattern noise (FPN) [
19], as shown in
Figure 15a,b). It makes it difficult to clarify the distinction of the range information. In order to reduce the FPN of the prototype APD, the off-chip digital offset adjustment was performed as in Refs. [
20,
21] so that the variation of APD can be reduced from 3.9 % to less than 0.1 % as shown in
Figure 16.
The total power consumption of the prototype receiver was measured as approximately 86 mW under the supply voltage of 1.8 V, which is dissipated by a 16-to-1 TICA into approximately 15.4 mW of power.
In this work, two types of response tests, the electrical response test and optical response test, were performed for verifying the prototype STUD-based LADAR receiver. The operation of the proposed 16-to-1 TICA receiver was only verified in an electrical response test with an electrical current pulse, and the prototype STUD-based LADAR sensor as a front-end circuit was verified for the largest area photodetector with CPDT of 32 pF through the PPC method.
Table 1 shows the performance summary of the prototype chip with a comparison to other works [
7,
11,
22,
23,
24,
25]. Compared to other works, the prototype of the proposed 16-to-1 TICA covers the largest area photodetector of 32 pF for high spatial resolution and worked well as the general TIA.
In the next step of this work, the full LADAR system will be implemented for real 3D imaging including a transmitter, time-to-digital converter (TDC), signal processor, etc. In order to enhance the accuracy of 3D information, the timing error compensation technique will be applied in the STUD receiver embedding the PPC method.