Next: 1.2 Three-Dimensional Integration Up: 1.1 Integration Technology Previous: 1.1.3 Interconnects in Integrated Circuits
Since transistor feature sizes and interconnect dimensions approach their physical limits expected at about the 5-7nm node, Moore's law will no longer be valid as the driving force for chip performance improvements [122,131]. The "more Moore" research domain introduces a new trend to work around the manufacturing and material limitations of silicon-based ICs by developing new technologies at the device level. These new transistor architectures are related to further scaling of complementary metal-oxide-semiconductor (CMOS) technologies, such as silicon on insulator (SOI) transistor and fin field electric transistor (FinFET), which use new materials, such as metal gates and high- dielectrics, to improve IC performance and continue scaling [131].
In addition to trying to go beyond the CMOS capabilities, the interconnect congestion in the circuit at the design and package levels is also a limiting factor, where interconnect RC delay dominates the overall scaling. By following a "more than Moore" approach, many researchers are attempting to incorporate multiple functionality beyond memory and logic on a single die. The functionality can involve sensors, radio-frequency (RF) circuitry, microelectromechanical systems (MEMS), among others and their integration. This approach requires new interconnect schemes based on a heterogeneous integration of various technologies in order to provide higher connectivity among circuit blocks located on different planes [122]. Examples of novel interconnection strategies are network on chip (NoC), optical interconnects, and 3D integration. The wide variety of opportunities and advantages that 3D integration offers to IC design is discussed in the following section. It should be pointed out that the functional diversification, offered by the "more than Moore" research domain, goes in parallel to the shrinking path provided by the "more Moore" approach.