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产品型号LTC2471IMS#TRPBF的概述

背景 LTC2471IMS#TRPBF是一款由Linear Technology(现为Analog Devices的一部分)制造的高性能24位模数转换器(ADC)。该芯片在精确度、噪声和采样率方面均表现优异,广泛应用于精准测量和信号处理领域。LTC2471 IMS#TRPBF以其低功耗和高分辨率,受到了工程师的青睐。 产品概述 LTC2471的主要功能是将模拟信号转换为数字信号。其独特的特点在于内置了一个低噪声、低漂移的增益放大器和一个高精度的内部基准电压源。这使得LTC2471能够在各种苛刻环境下有效工作,满足高精度测量的需求。 该芯片的输入电压范围很广,适用于多种信号调理方案。此外,LTC2471支持I2C接口,方便与微控制器和其他数字设备进行通信。其内置的数字滤波器和波形重建功能确保了最终输出信号的清晰度和可靠性。 详细参数 以下是LTC2471IMSTRPBF的主要技术参数:...

产品型号LTC2471IMS#TRPBF的Datasheet PDF文件预览

LTC2471/LTC2473  
Selectable 250sps/1ksps,  
2
16-Bit I C ΔΣ ADCs with 10ppm/°C  
Max Precision Reference  
DESCRIPTION  
FEATURES  
n
16-Bit Resolution, No Missing Codes  
TheLTC®2471/LTC2473aresmall,16-bitanalog-to-digital  
n
Internal, High Accuracy Reference—10ppm/°C (Max)  
Single-Ended (LTC2471) or Differential (LTC2473)  
Selectable 250sps/1ksps Output Rate  
1mV Offset Error  
converters with an integrated precision reference and  
a selectable 250sps or 1ksps output rate. They use a  
single 2.7V to 5.5V supply and communicate through an  
I2C Interface. The LTC2471 is single-ended with a 0V to  
VREF input range and the LTC2473 is differential with a  
VREF input range. Both ADC’s include a 1.25V integrated  
referencewith2ppm/°Cdriftperformanceand0.1%initial  
accuracy. The converters are available in a 12-pin DFN  
3mm × 3mm package or an MSOP-12 package. They  
include an integrated oscillator and perform conver-  
sions with no latency for multiplexed applications. The  
LTC2471/LTC2473 include a proprietary input sampling  
scheme that reduces the average input current several  
orders of magnitude when compared to conventional  
delta sigma converters.  
n
n
n
n
n
0.01% Gain Error  
Single Conversion Settling Time Simplifies  
Multiplexed Applications  
Single-Cycle Operation with Auto Shutdown  
3.5mA (Typ) Supply Current  
2μA (Max) Sleep Current  
n
n
n
n
Internal Oscillator—No External Components  
Required  
2
n
n
I C Interface  
Small 12-Lead, 3mm × 3mm DFN and MSOP  
Packages  
Following a single conversion, the LTC2471/LTC2473  
automatically power down the converter and can also be  
configured to power down the reference. When both the  
ADC and reference are powered down, the supply current  
is reduced to 200nA.  
APPLICATIONS  
n
System Monitoring  
n
Environmental Monitoring  
n
Direct Temperature Measurements  
n
Instrumentation  
The LTC2471/LTC2473 include a user selectable 250sps  
or 1ksps output rate and due to a large oversampling  
ratio (8,192 at 250sps and 2,048 at 1ksps) have relaxed  
anti-aliasing requirements.  
n
Industrial Process Control  
n
Data Acquisition  
n
Embedded ADC Upgrades  
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear  
Technology Corporation. All other trademarks are the property of their respective owners.  
Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.  
TYPICAL APPLICATION  
VREF vs Temperature  
1.2520  
2.7V TO 5.5V  
1.2515  
1.2510  
1.2505  
1.2500  
1.2495  
1.2490  
1.2485  
1.2480  
0.1μF  
0.1μF  
COMP  
0.1μF  
10μF  
0.1μF  
10k  
REFOUT  
V
CC  
SCL  
SDA  
+
2
IN  
I C  
INTERFACE  
10k  
10k  
LTC2473  
AO  
IN  
0.1μF  
REF  
GND  
R
24713 TA01a  
–50 –30 –10 10  
30  
50  
70  
90  
TEMPERATURE (°C)  
24713 TA01b  
24713f  
1
LTC2471/LTC2473  
ABSOLUTE MAXIMUM RATINGS  
(Notes 1, 2)  
Supply Voltage (V ) ................................... –0.3V to 6V  
Storage Temperature Range .................. –65°C to 150°C  
Operating Temperature Range  
CC  
Analog Input Voltage  
+
(V , V , V , V ,  
IN REF  
LTC2471C/LTC2473C ............................... 0°C to 70°C  
LTC2471I/LTC2473I..............................–40°C to 85°C  
IN  
IN  
V
, V  
) ...........................–0.3V to (V + 0.3V)  
COMP REFOUT CC  
Digital Voltage  
(V , V , V )..........................–0.3V to (V + 0.3V)  
SDA SCL AO  
CC  
PIN CONFIGURATION  
LTC2473  
LTC2473  
TOP VIEW  
TOP VIEW  
1
2
3
4
5
6
V
12  
CC  
REFOUT  
COMP  
AO  
1
2
3
4
5
6
REFOUT  
COMP  
AO  
12 V  
CC  
11 GND  
11 GND  
IN  
IN  
10  
9
13  
GND  
+
10 IN  
+
GND  
GND  
SCL  
SDA  
9
8
7
IN  
REF  
8
SCL  
REF  
GND  
7
GND  
SDA  
DD PACKAGE  
12-LEAD (3mm × 3mm) PLASTIC DFN  
MS PACKAGE  
12-LEAD PLASTIC MSOP  
T
JMAX  
= 125°C, θ = 130°C/W  
T
= 125°C, θ = 43°C/W  
JA  
JMAX  
JA  
EXPOSED PAD (PIN 13) PCB GROUND CONNECTION  
LTC2471  
LTC2471  
TOP VIEW  
TOP VIEW  
1
2
3
4
5
6
12  
V
CC  
REFOUT  
COMP  
AO  
1
2
3
4
5
6
REFOUT  
COMP  
AO  
12 V  
CC  
11 GND  
10 GND  
11 GND  
GND  
IN  
10  
9
13  
GND  
GND  
GND  
SCL  
SDA  
9
8
7
IN  
REF  
GND  
REF  
8
SCL  
7
GND  
SDA  
DD PACKAGE  
12-LEAD (3mm × 3mm) PLASTIC DFN  
MS PACKAGE  
12-LEAD PLASTIC MSOP  
T
JMAX  
= 125°C, θ = 130°C/W  
T
= 125°C, θ = 43°C/W  
JA  
JMAX  
JA  
EXPOSED PAD (PIN 13) PCB GROUND CONNECTION  
ORDER INFORMATION  
LEAD FREE FINISH  
LTC2471CDD#PBF  
LTC2471IDD#PBF  
LTC2471CMS#PBF  
LTC2471IMS#PBF  
LTC2473CDD#PBF  
LTC2473IDD#PBF  
LTC2473CMS#PBF  
LTC2473IMS#PBF  
TAPE AND REEL  
PART MARKING*  
LFPW  
PACKAGE DESCRIPTION  
TEMPERATURE RANGE  
0°C to 70°C  
LTC2471CDD#TRPBF  
LTC2471IDD#TRPBF  
LTC2471CMS#TRPBF  
LTC2471IMS#TRPBF  
LTC2473CDD#TRPBF  
LTC2473IDD#TRPBF  
LTC2473CMS#TRPBF  
LTC2473IMS#TRPBF  
12-Lead Plastic (3mm × 3mm) DFN  
12-Lead Plastic (3mm × 3mm) DFN  
12-Lead Plastic MSOP-12  
LFPW  
–40°C to 85°C  
0°C to 70°C  
2471  
2471  
12-Lead Plastic MSOP-12  
–40°C to 85°C  
0°C to 70°C  
LFPX  
12-Lead Plastic (3mm × 3mm) DFN  
12-Lead Plastic (3mm × 3mm) DFN  
12-Lead Plastic MSOP-12  
LFPX  
–40°C to 85°C  
0°C to 70°C  
2473  
2473  
12-Lead Plastic MSOP-12  
–40°C to 85°C  
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.  
Consult LTC Marketing for information on non-standard lead based finish parts.  
For more information on lead free part marking, go to: http://www.linear.com/leadfree/  
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/  
24713f  
2
LTC2471/LTC2473  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. (Note 2)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
l
Resolution (No Missing Codes)  
Integral Nonlinearity  
(Note 3)  
16  
Bits  
l
l
Output Rate 250sps (Note 4)  
Output Rate 1000sps (Note 4)  
2
8
8.5  
12  
LSB  
LSB  
l
Offset Error  
1
0.05  
0.01  
0.15  
3
2.5  
mV  
Offset Error Drift  
Gain Error  
LSB/°C  
l
l
0.25 % of FS  
LSB/°C  
Gain Error Drift  
Transition Noise  
Power Supply Rejection DC  
μV  
RMS  
80  
dB  
The l denotes the specifications which apply over the full operating temperature range, otherwise  
ANALOG INPUTS  
specifications are at TA = 25°C.  
SYMBOL  
PARAMETER  
CONDITIONS  
LTC2473  
MIN  
0
TYP  
MAX  
UNITS  
V
+
l
l
l
V
V
V
V
V
C
Positive Input Voltage Range  
Negative Input Voltage Range  
Input Voltage Range  
V
REF  
V
REF  
V
REF  
IN  
IN  
IN  
LTC2473  
0
V
LTC2471  
0
V
+
+
+
, V  
UR  
, V  
UR  
Overrange/Underrange Voltage, IN  
V
IN  
V
IN  
= 0.625V  
= 0.625V  
8
8
LSB  
LSB  
pF  
OR  
OR  
IN  
+
Overrange/Underrange Voltage, IN–  
+
IN , IN , IN Sampling Capacitance  
0.35  
+
l
l
+
I
IN , IN DC Leakage Current (LTC2473)  
IN DC Leakage Current (LTC2471)  
V
V
= GND (Note 8)  
–10  
–10  
1
1
10  
10  
nA  
nA  
DC_LEAK(IN , IN , IN)  
IN  
IN  
= V (Note 8)  
CC  
I
Input Sampling Current (Notes 5, 8)  
Reference Output Voltage  
50  
nA  
V
CONV  
l
l
V
1.247  
1.25  
1.253  
10  
REF  
Reference Voltage Coefficient  
(Note 9)  
C-Grade  
I-Grade  
2
5
ppm/°C  
ppm/°C  
Reference Line Regulation  
2.7V ≤ V ≤ 5.5V  
–90  
dB  
mA  
CC  
l
l
Reference Short Circuit Current  
COMP Pin Short Circuit Current  
Reference Load Regulation  
Reference Output Noise Density  
V
CC  
V
CC  
= 5.5, Forcing Output to GND (Note 8)  
= 5.5, Forcing Output to GND (Note 8)  
35  
200  
μA  
2.7V ≤ V ≤ 5.5V, I  
= 100ꢀA Sourcing  
= 0.1ꢀF, At f =  
3.5  
30  
mV/mA  
nV/√Hz  
CC  
OUT  
C
= 0.1ꢀF, C  
REFOUT  
COMP  
1ksps  
The l denotes the specifications which apply over the full operating temperature  
POWER REQUIREMENTS  
range, otherwise specifications are at TA = 25°C.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
l
V
CC  
Supply Voltage  
2.7  
5.5  
V
I
Supply Current  
Conversion  
Conversion  
Nap  
CC  
l
l
l
l
LTC2473 (Note 8)  
LTC2471 (Note 8)  
(Note 8)  
3.5  
2.5  
800  
0.2  
5
4
1500  
2
mA  
mA  
μA  
Sleep  
(Note 8)  
μA  
24713f  
3
LTC2471/LTC2473  
I2C INPUTS AND OUTPUTS  
The l denotes the specifications which apply over the full operating temperature  
range, otherwise specifications are at TA = 25°C. (Notes 2, 7)  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
0.7V  
TYP  
MAX  
UNITS  
V
l
l
l
l
l
l
l
l
l
l
V
V
High Level Input Voltage  
IH  
IL  
CC  
Low Level Input Voltage  
0.3V  
10  
V
CC  
I
Digital Input Current  
(Note 8)  
(Note 3)  
I = 3mA  
–10  
μA  
V
I
V
V
Hysteresis of Schmidt Trigger Inputs  
Low Level Output Voltage (SDA)  
Input Leakage  
0.05V  
HYS  
OL  
CC  
0.4  
1
V
I
0.1V ≤ V ≤ 0.9V  
CC  
μA  
pF  
pF  
V
IN  
CC  
IN  
C
C
V
V
Capacitance for Each I/O Pin  
Capacitance Load for Each Bus Line  
High Level Input Voltage for Address Pin  
Low Level Input Voltage for Address Pin  
10  
I
400  
B
0.95V  
IH(A0)  
IL(A0)  
CC  
0.05V  
V
CC  
I2C TIMING CHARACTERISTICS  
The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7)  
SYMBOL  
PARAMETER  
CONDITIONS  
SPD = 0  
MIN  
3.2  
0.8  
0
TYP  
4
MAX  
4.8  
UNITS  
ms  
ms  
kHz  
μs  
l
l
l
l
l
l
l
t
t
f
t
t
t
t
Conversion Time  
CONV1  
CONV2  
SCL  
Conversion Time  
SPD = 1  
1
1.2  
SCL Clock Frequency  
Hold Time (Repeated) START Condition  
LOW Period of the SCL Pin  
HIGH Period of the SCL Pin  
400  
0.6  
1.3  
0.6  
0.6  
HD(SDA,STA)  
LOW  
μs  
μs  
HIGH  
Set-Up Time for a Repeated START  
Condition  
μs  
SU(STA)  
l
l
l
l
l
l
t
t
t
t
t
t
Data Hold Time  
0
100  
0.9  
μs  
ns  
ns  
ns  
μs  
μs  
HD(DAT)  
Data Set-Up Time  
SU(DAT)  
Rise Time for SDA, SCL Signals  
Fall Time for SDA, SCL Signals  
Set-Up Time for STOP Condition  
(Note 6)  
(Note 6)  
20 + 0.1C  
20 + 0.1C  
0.6  
300  
300  
r
B
f
B
SU(STO)  
BUF  
Bus Free Time Between a Stop and Start  
Condition  
1.3  
l
l
t
t
Output Fall Time V  
to V  
Bus Load C = 10pF to 400pF (Note 6)  
20 + 0.1C  
250  
50  
ns  
ns  
OF  
SP  
IHMIN  
ILMAX  
B
B
Input Spike Suppression  
Note 5: Input sampling current is the average input current drawn from  
the input sampling network while the LTC2471/LTC2473 are converting.  
Note 1: Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to any Absolute  
Maximum Rating condition for extended periods may affect device  
reliability and lifetime.  
Note 6: C = capacitance of one bus line in pF.  
B
Note 7: All values refer to V  
) and V  
levels.  
IL(MAX)  
IH(MIN  
Note 2. All voltage values are with respect to GND. V = 2.7V to 5.5V  
CC  
Note 8: A positive current is flowing into the DUT pin.  
Note 9: Voltage temperature coefficient is calculated by dividing the  
maximum change in output voltage by the specified temperature range.  
unless otherwise specified.  
V
V
= V /2, FS = V , –V  
≤ V ≤ V  
REFCM  
REF  
REF  
REF  
IN  
REF  
+
+
= V – V , V  
= (V + V )/2. (LTC2473)  
IN  
IN  
IN  
INCM  
IN  
IN  
Note 3. Guaranteed by design, not subject to test.  
Note 4. Integral nonlinearity is defined as the deviation of a code from a  
straight line passing through the actual endpoints of the transfer curve.  
24713f  
4
LTC2471/LTC2473  
TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C, unless otherwise noted)  
Integral Nonlinearity  
Integral Nonlinearity  
Maximum INL vs Temperature  
3
2
3
2
6
4
V
CC  
= 2.7V  
OUTPUT RATE = 250sps  
T
A
= –45°C, 25°C, 90°C  
OUTPUT RATE = 250sps  
V
CC  
= 5.5V  
1
1
2
V
CC  
= 4.1V  
0
0
0
–1  
–2  
–3  
–1  
–2  
–3  
–2  
–4  
–6  
V
= 2.7V  
CC  
V
A
= 5.5V  
CC  
T
= –45°C, 25°C, 90°C  
OUTPUT RATE = 250sps  
–0.75 –0.25  
DIFFERENTIAL INPUT VOLTAGE (V)  
–1.25  
–0.75  
–0.25  
0.25  
0.75  
1.25  
–1.25  
0.25  
0.75  
1.25  
–50 –30 –10 10  
30  
50  
70  
90  
DIFFERENTIAL INPUT VOLTAGE (V)  
TEMPERATURE (°C)  
24713 G01  
24713 G03  
24713 G02  
Offset Error vs Temperature  
ADC Gain Error vs Temperature  
Transition Noise vs Temperature  
50  
40  
30  
20  
10  
0
10  
9
8
7
6
5
4
3
2
1
0
35  
30  
V
CC  
= 5.5V  
V
CC  
= 5.5V  
25  
20  
15  
10  
5
V
CC  
= 5.5V  
V
CC  
= 4.1V  
V
CC  
= 4.1V  
V
CC  
= 2.7V  
V
CC  
= 2.7V  
V
CC  
= 2.7V  
–10  
0
–50 –30 –10 10  
30  
50 70 90  
–50 –30 –10 10  
30  
50  
70  
90  
–50 –30 –10 10  
30  
50  
70  
90  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
24713 G05  
24713 G06  
24713 G04  
Conversion Mode Power Supply  
Current vs Temperature  
Sleep Mode Power Supply  
Current vs Temperature  
V
REF vs Temperature  
1.2508  
1.2507  
1.2506  
1.2505  
1.2504  
1.2503  
1.2502  
4.0  
3.9  
3.8  
3.7  
3.6  
3.5  
3.4  
3.3  
3.2  
3.1  
3.0  
350  
300  
250  
200  
150  
100  
50  
V
CC  
= 5.5V  
V
CC  
= 5.5V  
V
CC  
= 4.1V  
V
CC  
= 4.1V  
V
= 2.7V  
CC  
V
= 2.7V  
50  
CC  
0
–50 –30 –10 10  
30  
50  
70  
90  
–50 –30 –10 10  
30  
50  
70  
90  
–50 –30 –10 10  
30  
70  
90  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
24713 G09  
24713 G07  
24713 G08  
24713f  
5
LTC2471/LTC2473  
TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C, unless otherwise noted)  
Power Supply Rejection  
vs Frequency Applied to VCC  
Conversion Time vs Temperature  
VREF vs VCC  
4.4  
4.3  
4.2  
4.1  
4.0  
3.9  
3.8  
1.250345  
1.250340  
1.250335  
1.250330  
1.250325  
1.250320  
1.250315  
1.250310  
1.250305  
0
–20  
T
= 25°C  
A
T
= 25°C  
A
V
= 2.7V  
CC  
–40  
V
CC  
= 4.1V  
–60  
–80  
V
= 5.5V  
CC  
–100  
–120  
–50  
–25  
0
25  
50  
75  
100  
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0  
(V)  
1
10 100 1k 10k 100k 1M 10M  
TEMPERATURE (°C)  
V
FREQUENCY AT V (Hz)  
CC  
CC  
24713 G11  
24713 G12  
24713 G010  
PIN FUNCTIONS  
2
REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V,  
this voltage sets the full-scale input range of the ADC. For  
noise and reference stability connect to a 0.1μF capacitor  
tied to GND. This capacitor value must be less than or  
equal to the capacitor tied to the reference compensa-  
tion pin (COMP). REFOUT must not be overdriven by an  
external reference.  
SDA (Pin 6): Bidirectional Serial Data Line of the I C Inter-  
face. The conversion result is output through the SDA pin.  
The pin is high impedance unless the LTC2471/LTC2473  
is in the data output mode. While the LTC2471/LTC2473  
is in the data output mode, SDA is an open drain pull  
down (which requires an external 1.7k pull-up resistor  
to V ).  
CC  
COMP (Pin 2): Internal Reference Compensation Pin. For  
low noise and reference stability, tie a 0.1ꢀF capacitor to  
GND.  
REF (Pin 8): Negative Reference Input to the ADC. The  
voltage on this pin sets the zero input to the ADC. This  
pin should tie directly to ground or the ground sense of  
the input sensor.  
A0 (Pin 3): Chip Address Control Pin. The A0 pin can be  
+
tied to GND or V . If A0 is tied to GND, the LTC2471/  
IN (LTC2473), IN (LTC2471) (Pin 9): Positive input volt-  
age for the LTC2473 differential device. ADC input for the  
LTC2471 single-ended device.  
CC  
2
LTC2473 I C address is 0010100. If A0 is tied to V , the  
CC  
2
LTC2471/LTC2473 I C address is 1010100.  
GND (Pins 4, 7, 11, (Exposed Pad Pin 13 – DFN Package  
Only)):Ground.Connectexposedpaddirectlytotheground  
plane through a low impedance connection.  
IN (LTC2473), GND (LTC2471) (Pin 10): Negative input  
voltage for the LTC2473 differential device. GND for the  
LTC2471 single-ended device.  
2
SCL (Pin 5): Serial Clock Input of the I C Interface. The  
V
(Pin12):PositiveSupplyVoltage. BypasstoGNDwith  
CC  
2
LTC2471/LTC2473canonlyactasanI CslaveandtheSCL  
a 10ꢀF capacitor in parallel with a low-series-inductance  
0.1ꢀF capacitor located as close to pin 12 as possible.  
pin only accepts an external serial clock. Data is shifted  
into the SDA pin on the rising edges of SCL and output  
through the SDA pin on the falling edges of SCL.  
24713f  
6
LTC2471/LTC2473  
BLOCK DIAGRAM  
1
2
12  
REFOUT  
COMP  
V
CC  
3
A
O
INTERNAL  
REFERENCE  
5
6
ΔΣ A/D  
CONVERTER  
SPI  
INTERFACE  
SCL  
SDA  
9
+
IN  
(IN)  
DECIMATING  
SINC FILTER  
ΔΣ A/D  
CONVERTER  
10  
IN  
INTERNAL  
OSCILLATOR  
(GND)  
REF  
4, 7, 11, 13 DD PACKAGE  
4, 7, 11 MS PACKAGE  
GND  
8
24713 BD  
( ) PARENTHESIS INDICATE LTC2471  
Figure 1. Functional Block Diagram  
APPLICATIONS INFORMATION  
CONVERTER OPERATION  
POWER-ON RESET  
CONVERT  
Converter Operation Cycle  
The LTC2471/LTC2473 are low power, delta sigma, analog  
2
SLEEP/NAP  
to digital converters with a simple I C interface and a user  
selected 250sps/1ksps output rate (see Figure 1). The  
LTC2473 has a fully differential input while the LTC2471 is  
single-ended. Both are pin and software compatible. Their  
operation is composed of three distinct states: CONVERT,  
SLEEP/NAP, and DATA INPUT/OUTPUT. The operation  
begins with the CONVERT state (see Figure 2). Once the  
conversion is finished, the converter automatically pow-  
ers down (NAP) or under user control, both the converter  
andreferencearepowereddown(SLEEP).Theconversion  
result is held in a static register while the device is in this  
state. The cycle concludes with the DATA INPUT/OUTPUT  
state. Once all 16-bits are read or an abort is initiated, the  
device begins a new conversion.  
READ/WRITE  
NO  
ACKNOWLEDGE  
YES  
DATA INPUT/OUTPUT  
STOP  
OR  
READ 16 BITS  
NO  
YES  
24713 F02  
The CONVERT state duration is determined by the  
LTC2471/LTC2473 conversion time (nominally 4ms or  
1ms depending on the selected output rate). Once started,  
this operation can not be aborted except by a low power  
Figure 2. LTC2471/LTC2473 State Transition Diagram  
supply condition (V < 2.1V) which generates an internal  
CC  
power-on reset signal.  
24713f  
7
LTC2471/LTC2473  
APPLICATIONS INFORMATION  
Afterthecompletionofaconversion,theLTC2471/LTC2473  
enterstheSLEEP/NAPstateandremainsthereuntilavalid  
read/write is acknowledged. Following this condition, the  
ADC transitions into the DATA INPUT/OUTPUT state.  
approximately 0.5ms. For proper operation V needs  
DD  
to be restored to normal operating range (2.7V to 5.5V)  
before the conclusion of the POR cycle. The POR signal  
clears all internal registers. Following the POR signal, the  
LTC2471/LTC2473 start a conversion cycle and follow the  
succession of states shown in Figure 2. The reference  
While in the SLEEP/NAP state, the LTC2471/LTC2473’s  
converters are powered down. This reduces the supply  
current by approximately 70%. While in the NAP state the  
reference remains powered up. The user can power down  
both the reference and the converter by enabling the sleep  
modeduringtheDATAINPUT/OUTPUTstate.Oncethenext  
conversion is complete with the sleep mode enabled, the  
SLEEPstateisenteredandpowerisreducedto2A(maxi-  
mum).Thereferenceispowereduponceavalidread/write  
is acknowledged. The reference startup time is 12ms (if  
the reference and compensation capacitor values are both  
0.1ꢀF). As the reference and compensation capacitors are  
decreased, the startup time is reduced (see Figure 3), but  
the transition noise increases (see Figure 4).  
startup time following a POR is 12ms (C  
= C  
=
COMP  
REFOUT  
0.1ꢀF). The first conversion following power-up will be  
invalid if the reference voltage has not completely settled  
(see Figure 3). The first conversion following power up  
can be discarded using the data abort command or sim-  
ply read and ignored. Depending on the value chosen for  
C
and C  
, the reference startup can take more  
COMP  
REFOUT  
than one conversion period, see Figure 3. If the startup  
time is less than 1ms (1ksps output rate) or 4ms (250sps  
outputrate)thenconversionsfollowingtherstperiodare  
accurate to the device specifications. If the startup time  
exceeds1msor4msthentheusercanwaittheappropriate  
time or use the fixed conversion period as a startup timer  
by ignoring results within the unsettled period. Once the  
reference has settled, all subsequent conversion results  
are valid. If the user places the device into the sleep mode  
(SLP = 1, reference powered down) the reference will  
Power-Up Sequence  
When the power supply voltage (V ) applied to the con-  
CC  
verter is below approximately 2.1V, the ADC performs a  
power-on reset. This feature guarantees the integrity of  
the conversion result.  
require a startup time proportional to the value of C  
and C  
COMP  
(see Figure 3).  
REFOUT  
WhenV risesabovethiscriticalthreshold, theconverter  
CC  
generates an internal power-on reset (POR) signal for  
25  
20  
15  
10  
5
250  
200  
V
CC  
= 2.7V  
150  
100  
50  
V
= 4.1V  
CC  
0
V
CC  
= 5.5V  
0
0.0001 0.001  
0.01  
0.1  
1
10  
CAPACITANCE (μF)  
24713 F04  
–50  
1
0.1  
0.01  
0.001  
Figure 4. Transition Noise RMS vs COMP and  
Reference Capacitance  
CAPACITANCE (μF)  
24713 F03  
Figure 3. Reference Start-Up Time vs VREF and  
Compensation Capacitance  
24713f  
8
LTC2471/LTC2473  
APPLICATIONS INFORMATION  
Ease of Use  
2
I C INTERFACE  
2
The LTC2471/LTC2473 data output has no latency, filter  
settling delay, or redundant results associated with the  
conversion cycle. There is a one-to-one correspondence  
between the conversion and the output data. Therefore,  
multiplexing multiple analog input voltages requires no  
special actions.  
The LTC2471/LTC2473 communicate through an I C in-  
2
terface. The I C interface is a 2-wire open-drain interface  
supporting multiple devices and masters on a single bus.  
The connected devices can only pull the data line (SDA)  
LOW and can never drive it HIGH. SDA must be externally  
connected to the supply through a pull-up resistor. When  
2
the data line is free, it is HIGH. Data on the I C bus can be  
transferredatratesupto100kbits/sintheStandard-Mode  
and up to 400kbits/s in the Fast-Mode.  
TheLTC2471/LTC2473includeaproprietaryinputsampling  
scheme that reduces the average input current by several  
orders of magnitude when compared to traditional delta-  
sigma architectures. This allows external filter networks  
to interface directly to the LTC2471/LTC2473. Since the  
average input sampling current is 50nA, an external RC  
lowpass filter using 1kΩ and 0.1μF results in <1LSB  
additional error. Additionally, there is negligible leakage  
UponenteringtheDATAINPUT/OUTPUTstate,SDAoutputs  
the sign (D15) of the conversion result. During this state,  
the ADC shifts the conversion result serially through the  
SDA output pin under the control of the SCL input pin.  
There is no latency in generating this data and the result  
corresponds to the last completed conversion. A new bit  
of data appears at the SDA pin following each falling edge  
detectedattheSCLinputpinandappearsfromMSBtoLSB.  
The user can reliably latch this data on every rising edge  
of the external serial clock signal driving the SCL pin.  
+
current between IN and IN (for the LTC2473).  
Input Voltage Range (LTC2471)  
Ignoring offset and full-scale errors, the LTC2471 will  
theoretically output an “all zero” digital result when the  
input is at ground (a zero scale input) and an “all one”  
2
Each device on the I C bus is recognized by a unique  
digital result when the input is at V or higher (V  
REF  
REFOUT  
address stored in that device and can operate either as  
a transmitter or receiver, depending on the function of  
the device. In addition to transmitters and receivers,  
devices can also be considered as masters or slaves when  
performing data transfers. A master is the device which  
initiates a data transfer on the bus and generates the  
clock signals to permit that transfer. Devices addressed  
by the master are considered a slave. The address of the  
LTC2471/LTC2473 is 0010100 (if A0 is tied to GND) or  
=1.25V).Inanunderrangecondition(forallinputvoltages  
below zero scale) the converter will generate the output  
code 0. In an overrange condition (for all input voltages  
greater than V ) the converter will generate the output  
REF  
code 65535.  
Input Voltage Range (LTC2473)  
As detailed in the Output Data Format section, the output  
+
codeisgivenasINT(32767.5(V V )/V +32767.5.  
1010100 (if A0 is tied to V ).  
IN  
IN  
REF  
CC  
+
For (V – V ) ≥ V , the output code is clamped at  
IN  
IN  
REF  
+
65535 (all ones). For (V – V ) ≤ –V , the output  
IN  
IN  
REF  
code is clamped at 0 (all zeroes).  
24713f  
9
LTC2471/LTC2473  
APPLICATIONS INFORMATION  
Data Transferring  
The LTC2471/LTC2473 can only be addressed as a slave.  
It can only transmit the last conversion result. The serial  
clockline,SCL,isalwaysaninputtotheLTC2471/LTC2473  
andtheserialdatalineSDAisbidirectional.Figure5shows  
2
After the START condition, the I C bus is busy and data  
transfer can begin between the master and the addressed  
slave. Data is transferred over the bus in groups of nine  
bits, one byte followed by one acknowledge (ACK) bit. The  
master releases the SDA line during the ninth SCL clock  
cycle. The slave device can issue an ACK by pulling SDA  
LOW or issue a Not Acknowledge (NAK) by leaving the  
SDA line HIGH impedance (the external pull-up resistor  
will hold the line HIGH). Change of data only occurs while  
the clock line (SCL) is LOW.  
2
the definition of the I C timing.  
The START and STOP Conditions  
A START (S) condition is generated by transitioning SDA  
from HIGH to LOW while SCL is HIGH. The bus is consid-  
ered to be busy after the START condition. When the data  
transfer is finished, a STOP (P) condition is generated by  
transitioning SDA from LOW to HIGH while SCL is HIGH.  
ThebusisfreeafteraSTOPisgenerated.STARTandSTOP  
conditions are always generated by the master.  
Output Data Format  
After a START condition, the master sends a 7-bit address  
followed by a read request (R) bit. The bit R is 1 for a  
Read Request. If the 7-bit address matches the LTC2471/  
LTC2473’saddress(0010100or1010100,dependingonthe  
state of the pin A0) the ADC is selected. When the device is  
addressed during the conversion state, it does not accept  
When the bus is in use, it stays busy if a repeated START  
(Sr)isgeneratedinsteadofaSTOPcondition.Therepeated  
START timing is functionally identical to the START and  
is used for reading from the device before the initiation  
of a new conversion.  
SDA  
t
SU(DAT)  
t
r
t
r
t
f
t
t
t
t
BUF  
t
f
HD(SDA)  
SP  
LOW  
SCL  
t
t
t
SU(STO)  
HD(STA)  
SU(STA)  
t
t
HIGH  
S
Sr  
P
S
HD(DAT)  
24713 F05  
Figure 5. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus  
24713f  
10  
LTC2471/LTC2473  
APPLICATIONS INFORMATION  
therequestandissuesaNAKbyleavingtheSDAlineHIGH.  
If the conversion is complete, the LTC2471/LTC2473 issue  
an ACK by pulling the SDA line LOW.  
The LTC2473 (differential input) output code is given by  
+
INT(32767.5 • (V – V )/V + 32767.5. The first bit  
IN  
IN  
REF  
output by the LTC2473, D15, is the MSB, which is 1 for  
+
+
V
IN  
≥ V and 0 for V < V . This bit is followed by  
IN IN IN  
FollowingtheACK, theLTC2471/LTC2473canoutputdata.  
The data output stream is 16 bits long and is shifted out  
on the falling edges of SCL (see Figure 6).  
successively less significant bits (D14, D13, …) until the  
LSB is output by the LTC2473, see Table 1.  
The LTC2471 (single-ended input) output code is a direct  
binary encoded result, see Table 1.  
The DATA INPUT/OUTPUT state is concluded once all 16  
data bits have been read or after a STOP condition.  
Table 1. LTC2471/LTC2473 Output Data Format  
SINGLE ENDED INPUT V  
(LTC2471)  
DIFFERENTIAL INPUT VOLTAGE  
D15  
(MSB)  
D14  
D13  
D12...D2  
D1  
D0  
(LSB)  
CORRESPONDING  
DECIMAL VALUE  
IN  
+
V
– V (LTC2473)  
IN  
IN  
≥V  
≥V  
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
65535  
65534  
49152  
49151  
32768  
32767  
16384  
16383  
0
REF  
REF  
V
– 1LSB  
V
– 1LSB  
REF  
REF  
0.75 • V  
0.5 • V  
REF  
REF  
0.75 • V – 1LSB  
0.5 • V – 1LSB  
REF  
REF  
0.5 • V  
0
REF  
0.5 • V – 1LSB  
–1LSB  
REF  
0.25 • V  
–0.5 • V  
REF  
REF  
0.25 • V – 1LSB  
–0.5 • V – 1LSB  
REF  
REF  
0
≤ –V  
REF  
1
7
8
9
1
2
3
8
9
1
2
3
8
9
SCL  
SDA  
7-BIT  
ADDRESS  
R
D15  
D14  
D13  
D8  
D7  
D6  
D5  
D0  
MSB  
LSB  
START BY  
MASTER  
ACK BY  
LTC2471/LTC2473  
ACK BY  
MASTER  
NACK BY  
MASTER  
SLEEP  
DATA OUTPUT  
CONVERSION  
24713 F06  
Figure 6. Read Sequence Timing Diagram  
24713f  
11  
LTC2471/LTC2473  
APPLICATIONS INFORMATION  
The sleep bit (SLP) is used to power down the on chip  
reference. In the default mode, the reference remains  
powered up even when the ADC is powered down. If the  
SLP bit is set HIGH, the reference will power down after  
the next conversion is complete. It will remain powered  
downuntilavalidaddressisacknowledged. Thereference  
startup time is approximately 12ms. In order to ensure a  
stable reference for the following conversions, either the  
data input/output time should be delayed 12ms after an  
address acknowledge or the first conversion following a  
reference start up should be discarded.  
Data Input Format  
After a START condition, the master sends a 7-bit ad-  
dress followed by a read/write request (R/W) bit. The  
R/W bit is 0 for a write. The data input word is 4 bits long  
and consists of two enable bits (EN1 and EN2) and two  
programming bits (SPD and SLP), see Figure 7. EN1 is  
applied to the first rising edge of SCL after a valid write  
address is acknowledged. Programming is enabled by  
setting EN1 = 1 and EN2 = 0.  
The speed bit (SPD) determines the output rate, SPD = 0  
(default) for a 250sps and SPD = 1 for a 1ksps output  
rate. The sleep bit (SLP) is used to power down the  
on-chip reference. In the default mode, the reference re-  
mains powered up at the conclusion of each conversion  
cycle while the ADC is automatically powered down at the  
end of each conversion cycle. If the SLP bit is set HIGH,  
thereferenceandtheADCarepowereddownoncethenext  
conversion cycle is completed. The reference and ADC are  
poweredupagainonceavalidread/writeisacknowledged.  
The following conversion is invalid if the next conversion  
is started before the reference has started up (see Figure 3  
for reference startup times as a function of compensation  
capacitor and reference capacitor).  
Table 2. Input Data Format  
BIT NAME FUNCTION  
EN1  
EN2  
SPD  
Should Be High (EN1 = 1) in Order to Enable Program Mode  
Should Be Low (EN2 = 0) in Order to Enable Program Mode  
Low (SPD = 0, Default) for 250sps, High (SPD = 1) for 1ksps  
Output Rate  
SLP  
Low (SLP = 0, Default) for Nap Mode, High (SLP = 1)  
for Sleep Mode Where Both Reference and Converter are  
Powered Down  
1
2
7
8
9
1
2
3
4
5
6
7
8
9
SCL  
SDA  
7-BIT ADDRESS  
EN1  
EN2  
SPD  
SLP  
W
ACK BY  
LTC2471/LTC2473  
ACK BY  
LTC2471/LTC2473  
START BY  
MASTER  
SLEEP  
DATA INPUT  
24713 F07  
Figure 7. Timing Diagram for Writing to the LTC2471/LTC2473  
24713f  
12  
LTC2471/LTC2473  
APPLICATIONS INFORMATION  
OPERATION SEQUENCE  
signal indicating the conversion cycle is in progress. See  
Figure 9 for an example state diagram.  
Continuous Read  
Discarding a Conversion Result and Initiating a New  
Conversion  
Conversions from the LTC2471/LTC2473 can be continu-  
ously read, see Figure 8. The R/W is 1 for a read. At the  
end of a read operation, a new conversion automatically  
begins. At the conclusion of the conversion cycle, the next  
result may be read using the method described above. If  
the conversion cycle is not complete and a valid address  
selects the device, the LTC2471/LTC2473 generate a NAK  
It is possible to start a new conversion without reading  
the old result, as shown in Figure 10. Following a valid  
7-bit address, a read request (R/W) bit, and a valid ACK,  
a STOP command will start a new conversion.  
7-BIT ADDRESS  
(0010100 OR 1010100)  
7-BIT ADDRESS  
(0010100 OR 1010100)  
S
R
ACK  
READ  
P
S
R
ACK  
READ  
P
SLEEP  
DATA OUTPUT  
CONVERSION  
SLEEP  
DATA OUTPUT  
CONVERSION  
CONVERSION  
24713 F08  
Figure 8. Consecutive Reading  
WRITE INPUT  
CONFIGURATION  
(FIGURE 7)  
ACK  
7-BIT ADDRESS:  
0010100 OR 1010100  
R/W  
BIT LOW  
2
I C START  
2
I C STOP  
CONVERT  
CONVERSION  
FINISHED  
WRITE INPUT  
CONFIGURATION  
(FIGURE 7)  
R/W  
BIT LOW  
7-BIT ADDRESS:  
0010100 OR 1010100  
2
2
I C (REPEAT) START  
I C START  
FOR CYCLE N  
CONVERSION  
FINISHED  
ACK  
NAK  
7-BIT ADDRESS:  
0010100 OR 1010100  
R/W  
BIT HIGH  
READ DATA FROM  
CYCLE N-1  
2
I C STOP  
CONVERT  
24713 F09  
ACK  
Figure 9. I2C State Diagram  
7-BIT ADDRESS  
S
R
ACK READ (OPTIONAL)  
DATA OUTPUT  
P
(0010100 OR 1010100)  
CONVERSION  
SLEEP  
CONVERSION  
24713 F10  
Figure 10. Start a New Conversion without Reading Old Conversion Result  
24713f  
13  
LTC2471/LTC2473  
APPLICATIONS INFORMATION  
PRESERVING THE CONVERTER ACCURACY  
The V pin should have two distinct connections: the  
CC  
first to the decoupling capacitors described above, and  
the second to the ground return for the power supply  
voltage source.  
TheLTC2471/LTC2473aredesignedtominimizetheconver-  
sion result’s sensitivity to device decoupling, PCB layout,  
anti-aliasing circuits, line and frequency perturbations.  
Nevertheless,inordertopreservethehighaccuracycapabil-  
ity of this part, some simple precautions are desirable.  
REFOUT and COMP  
The on chip 1.25V reference is internally tied to the  
converter’s reference input and is output to the REFOUT  
pin. A 0.1ꢀF capacitor should be placed on the REFOUT  
pin.Itispossibletoreducethiscapacitor,butthetransition  
noise increases (see Figure 4). A 0.1ꢀF capacitor should  
also be placed on the COMP pin. This pin is tied to an  
internal point in the reference and is used for stability.  
In order for the reference to remain stable, the capacitor  
placed on the COMP pin must be greater than or equal  
to the capacitor tied to the REFOUT pin. The REFOUT pin  
cannot be overridden by an external voltage.  
Digital Signal Levels  
DuetothenatureofCMOSlogic,itisadvisabletokeepinput  
digital signals near GND or V . Voltages in the range of  
CC  
0.5V to V – 0.5V may result in additional current leakage  
CC  
from the part. Undershoot and overshoot should also be  
minimized, particularly while the chip is converting. It is  
thus beneficial to keep edge rates of about 10ns and limit  
overshoot and undershoot to less than 0.3V.  
Driving V and GND  
CC  
DependingonthesizeofthecapacitorstiedtotheREFOUT  
andCOMPpins,theinternalreferencehasacorresponding  
start up time. This start up time is typically 12ms when  
InrelationtotheV andGNDpins, the LTC2471/LTC2473  
CC  
combinesinternalhighfrequencydecouplingwithdamping  
elements, which reduce the ADC performance sensitivity  
to PCB layout and external components. Nevertheless,  
the very high accuracy of this converter is best pre-  
served by careful low and high frequency power supply  
decoupling.  
INTERNAL  
REFERENCE  
V
CC  
R
SW  
15k  
(TYP)  
I
I
LEAK  
REFOUT  
LEAK  
A 0.1μF, high quality, ceramic capacitor in parallel with  
a 10μF low ESR ceramic capacitor should be connected  
V
V
V
CC  
CC  
CC  
R
IN  
SW  
between the V and GND pins, as close as possible to the  
CC  
15k  
(LTC2471)  
I
I
LEAK  
(TYP)  
+
package. The 0.1μF capacitor should be placed closest  
IN  
(LTC2473)  
to the ADC package. It is also desirable to avoid any via  
LEAK  
in the circuit path, starting from the converter V pin,  
CC  
passing through these two decoupling capacitors, and  
returningtotheconverterGNDpin.Theareaencompassed  
by this circuit path, as well as the path length, should be  
minimized.  
C
EQ  
R
SW  
0.35pF  
(TYP)  
15k  
I
I
LEAK  
(TYP)  
IN  
(LTC2473)  
LEAK  
As shown in Figure 11, REF is used as the negative  
reference voltage input to the ADC. This pin can be tied  
directly to ground or Kelvin sensed to sensor ground. In  
R
SW  
15k  
I
I
LEAK  
(TYP)  
24713 F11  
REF  
the case where REF is used as a sense input, it should  
LEAK  
be bypassed to ground with a 0.1ꢀF ceramic capacitor in  
parallel with a 10ꢀF low ESR ceramic capacitor.  
Figure 11. LTC2471/LTC2473 Analog Input/Reference  
Equivalent Circuit  
Very low impedance ground and power planes, and star  
connections at both V and GND pins, are preferable.  
CC  
24713f  
14  
LTC2471/LTC2473  
APPLICATIONS INFORMATION  
0.1ꢀF capacitors are used. The first conversion following  
power up can be discarded using the data abort com-  
mand or simply read and ignored. Depending on the value  
PCBlayout, C hastypicalvaluesbetween2pFand15pF.  
PAR  
In addition, the equivalent circuit of Figure 12 includes the  
converter equivalent internal resistor R and sampling  
SW  
chosen for C  
and C , the reference startup can  
REFOUT  
capacitor C .  
COMP  
EQ  
take more than one conversion period, see Figure 3. If  
the startup time is less than 1ms (1ksps output rate) or  
4ms (250sps output rate) then conversions following the  
first period are accurate to the device specifications. If the  
startup time exceeds 1ms or 4ms then the user can wait  
the appropriate time or use the fixed conversion period  
as a startup timer by ignoring results within the unsettled  
period. Once the reference has settled all subsequent  
conversion results are valid. If the user places the device  
into the sleep mode (SLP = 1, reference powered down)  
the reference will require a startup time proportional to  
Therearesomeimmediatetrade-offsinR andC without  
S
IN  
needing a full circuit analysis. Increasing R and C can  
S
IN  
give the following benefits:  
1) Due to the LTC2471/LTC2473’s input sampling algo-  
+
rithm, the input current drawn by either IN or IN over  
a conversion cycle is typically 50nA. A high R • C  
S
IN  
attenuates the high frequency components of the input  
current, and R values up to 1k result in <1LSB error.  
S
2) The bandwidth from V is reduced at the input pins  
SIG  
+
(IN , IN or IN). This bandwidth reduction isolates the  
ADCfromhighfrequencysignals, andassuchprovides  
simple anti-aliasing and input noise reduction.  
the value of C  
and C  
, see Figure 3.  
COMP  
REFOUT  
If the reference is put to sleep (program SLP = 1 and CS =  
1)thereferenceispowereddownafterthenextconversion.  
This last conversion result is valid. On CS falling edge,  
the reference is powered back up. In order to ensure the  
reference output has settled before the next conversion,  
the power up time can be extended by delaying the data  
read after the falling edge of CS. Once all 16 bits are read  
from the device or CS is brought HIGH, the next conver-  
sion automatically begins. In the default operation, the  
reference remains powered up at the conclusion of the  
conversion cycle.  
3) Switching transients generated by the ADC are attenu-  
ated before they go back to the signal source.  
4) A large C gives a better AC ground at the input pins,  
IN  
helping reduce reflections back to the signal source.  
5) Increasing R protects the ADC by limiting the current  
S
during an outside-the-rails fault condition.  
V
V
CC  
IN  
R
SW  
(LTC2471)  
15k  
I
LEAK  
R
(TYP)  
S
+
+
IN  
Driving V and V  
IN  
IN  
(LTC2473)  
I
LEAK  
+
C
C
C
+
IN  
EQ  
SIG  
SIG  
I
CONV  
The input drive requirements can best be analyzed using  
0.35pF  
(TYP)  
C
PAR  
the equivalent circuit of Figure 12. The input signal V is  
SIG  
+
connected to the ADC input pins (IN and IN ) through an  
CC  
R
SW  
15k  
equivalentsourceresistanceR .Thisresistorincludesboth  
I
LEAK  
S
R
S
(TYP)  
IN  
(LTC2473)  
the actual generator source resistance and any additional  
I
LEAK  
C
+
IN  
optional resistors connected to the input pins. Optional  
EQ  
I
CONV  
0.35pF  
(TYP)  
C
PAR  
input capacitors C are also connected to the ADC input  
IN  
24713 F12  
pins. This capacitor is placed in parallel with the input  
parasitic capacitance C . This parasitic capacitance  
PAR  
Figure 12. LTC2471/LTC2473 Input Drive Equivalent Circuit  
includes elements from the printed circuit board (PCB)  
and the associated input pin of the ADC. Depending on the  
24713f  
15  
LTC2471/LTC2473  
APPLICATIONS INFORMATION  
There is a limit to how large R • C should be for a given  
ments, low impedance voltage source monitoring, and so  
S
IN  
application. Increasing R beyond a given point increases  
on. The resultant INL vs V is shown in Figure 14. The  
S
IN  
the voltage drop across R due to the input current,  
measurements of Figure 14 include a capacitor C  
cor-  
S
PAR  
to the point that significant measurement errors exist.  
Additionally, forsomeapplications, increasingtheR •C  
respondingtoaminimumsizedlayoutpadandaminimum  
width input trace of about 1 inch length.  
S
IN  
product too much may unacceptably attenuate the signal  
at frequencies of interest.  
Signal Bandwidth, Transition Noise and Noise  
Equivalent Input Bandwidth  
For most applications, it is desirable to implement C as  
IN  
2
TheLTC2471/LTC2473includeasinc typedigitallter.The  
a high-quality 0.1μF ceramic capacitor and to set R ≤  
S
first notch is located at 500Hz if the 250sps output rate is  
selected and 2kHz if the 1ksps output rate is selected. The  
calculated input signal attenuation vs. frequency over a  
widefrequencyrangeisshowninFigure15.Thecalculated  
input signal attenuation vs. frequency at low frequencies  
is shown in Figure 16. The converter noise level is about  
1k. This capacitor should be located as close as possible  
+
to the actual IN , IN and IN package pins. Furthermore,  
the area encompassed by this circuit path, as well as the  
path length, should be minimized.  
In the case of a 2-wire sensor that is not remotely  
grounded, it is desirable to split R and place series  
S
3μV  
and can be modeled by a white noise source con-  
RMS  
resistors in the ADC input line as well as in the sensor  
ground return line, which should be tied to the ADC GND  
pin using a star connection topology.  
nected at the input of a noise-free converter.  
On a related note, the LTC2473 uses two separate A/D  
converters to digitize the positive and negative inputs.  
Figure 13 shows the measured LTC2473 INL vs Input  
EachoftheseA/Dconvertershas3μV  
transitionnoise.  
RMS  
Voltage as a function of R value with an input capacitor  
S
If one of the input voltages is within this small transition  
noise band, then the output will fluctuate one bit, regard-  
less of the value of the other input voltage. If both of the  
input voltages are within their transition noise bands, the  
output can fluctuate 2 bits.  
C = 0.1μF.  
IN  
Insomecases,R canbeincreasedabovetheseguidelines.  
S
The input current is zero when the ADC is either in sleep  
or I/O modes. Thus, if the time constant of the input RC  
circuit τ = R • C , is of the same order of magnitude or  
S
IN  
Forasimplesystemnoiseanalysis,theV drivecircuitcan  
IN  
longer than the time periods between actual conversions,  
then one can consider the input current to be reduced  
correspondingly.  
be modeled as a single-pole equivalent circuit character-  
ized by a pole location f and a noise spectral density n .  
i
i
If the converter has an unlimited bandwidth, or at least a  
These considerations need to be balanced out by the input  
bandwidth substantially larger than f , then the total noise  
i
signal bandwidth. The 3dB bandwidth ≈ 1/(2πR C ).  
contribution of the external drive circuit would be:  
S IN  
Finally, if the recommended choice for C is unacceptable  
IN  
Vn = ni π /2• fi  
fortheuser’sspecificapplication,analternatestrategyisto  
eliminateC andminimizeC andR .Inpracticalterms,  
IN  
PAR  
S
Then, the total system noise level can be estimated as  
2
thisconfigurationcorrespondstoalowimpedancesensor  
directly connected to the ADC through minimum length  
traces. Actual applications include current measurements  
through low value sense resistors, temperature measure-  
the square root of the sum of (V ) and the square of the  
n
LTC2471/LTC2473 noise floor.  
24713f  
16  
LTC2471/LTC2473  
APPLICATIONS INFORMATION  
6
6
C
V
T
= 0.1μF  
= 5V  
C
V
T
= 0  
IN  
CC  
IN  
CC  
A
5
4
= 5V  
= 25°C  
= 25°C  
4
2
A
R
S
= 1k  
3
2
R
S
= 1k  
1
0
0
R
= 0k  
–2  
–4  
–6  
S
–1  
–2  
–3  
–4  
R
= 0k  
S
–1.25  
–0.75  
–0.25  
0.25  
0.75  
1.25  
–1.25  
–0.75  
–0.25  
0.25  
0.75  
1.25  
DIFFERENTIAL INPUT VOLTAGE (V)  
DIFFERENTIAL INPUT VOLTAGE (V)  
24713 F13  
24713 F14  
Figure 13. Measured INL vs Input Voltage  
Figure 14. Measured INL vs Input Voltage  
0
–20  
0
–20  
–40  
–40  
–60  
–60  
–80  
–80  
–100  
–120  
–140  
–100  
–120  
–140  
0
10  
15  
20  
5
0
1000  
2000  
3000  
4000  
5000  
INPUT SIGNAL FREQUENCY (Hz)  
INPUT SIGNAL FREQUENCY (MHz)  
24713 F15  
24713 F16  
Figure 15. LTC2473 Input Signal Attenuation vs  
Frequency (250sps Mode)  
Figure 16. LTC2473 Input Signal Attenuation vs  
Frequency (250sps Mode)  
0
–20  
0
–20  
–40  
–40  
–60  
–60  
–80  
–80  
–100  
–120  
–140  
–100  
–120  
–140  
0
5
10  
15  
20  
0
5
10  
15  
20  
INPUT SIGNAL FREQUENCY (MHz)  
INPUT SIGNAL FREQUENCY (kHz)  
24713 F17  
24713 F18  
Figure 18. LTC2473 Input Signal Attenuation vs  
Frequency (1000sps Mode)  
Figure 17. LTC2473 Input Signal Attenuation vs  
Frequency (1000sps Mode)  
24713f  
17  
LTC2471/LTC2473  
PACKAGE DESCRIPTION  
MS Package  
12-Lead Plastic MSOP  
(Reference LTC DWG # 05-08-1668 Rev Ø)  
4.039 p 0.102  
(.159 p .004)  
(NOTE 3)  
0.889 p 0.127  
(.035 p .005)  
0.406 p 0.076  
(.016 p .003)  
REF  
12 11 10 9 8 7  
DETAIL “A”  
0.254  
3.00 p 0.102  
(.118 p .004)  
(NOTE 4)  
5.23  
4.90 p 0.152  
(.193 p .006)  
3.20 – 3.45  
(.206)  
(.126 – .136)  
MIN  
(.010)  
0o – 6o TYP  
GAUGE PLANE  
0.53 p 0.152  
(.021 p .006)  
1
2 3 4 5 6  
0.65  
(.0256)  
BSC  
0.42 p 0.038  
(.0165 p .0015)  
TYP  
0.86  
(.034)  
REF  
1.10  
(.043)  
MAX  
DETAIL “A”  
0.18  
(.007)  
SEATING  
PLANE  
RECOMMENDED SOLDER PAD LAYOUT  
0.22 – 0.38  
(.009 – .015)  
TYP  
0.1016 p 0.0508  
(.004 p .002)  
MSOP (MS12) 1107 REV Ø  
0.650  
(.0256)  
BSC  
NOTE:  
1. DIMENSIONS IN MILLIMETER/(INCH)  
2. DRAWING NOT TO SCALE  
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.  
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE  
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.  
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE  
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX  
24713f  
18  
LTC2471/LTC2473  
PACKAGE DESCRIPTION  
DD Package  
12-Lead Plastic DFN (3mm × 3mm)  
(Reference LTC DWG # 05-08-1725 Rev A)  
R = 0.115  
0.40 0.10  
TYP  
7
12  
0.70 0.05  
2.38 0.10  
1.65 0.10  
2.38 0.05  
1.65 0.05  
3.50 0.05  
2.10 0.05  
3.00 0.10  
(4 SIDES)  
PACKAGE  
OUTLINE  
PIN 1 NOTCH  
R = 0.20 OR  
0.25 s 45°  
CHAMFER  
PIN 1  
TOP MARK  
(SEE NOTE 6)  
6
1
0.23 0.05  
0.45 BSC  
0.75 0.05  
0.200 REF  
0.25 0.05  
0.45 BSC  
2.25 REF  
(DD12) DFN 0106 REV A  
2.25 REF  
0.00 – 0.05  
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS  
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED  
BOTTOM VIEW—EXPOSED PAD  
NOTE:  
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE  
2. DRAWING NOT TO SCALE  
3. ALL DIMENSIONS ARE IN MILLIMETERS  
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE  
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE  
5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED  
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE  
TOP AND BOTTOM OF PACKAGE  
24713f  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-  
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.  
19  
LTC2471/LTC2473  
TYPICAL APPLICATION  
10μF  
V
V
CC  
CC  
V
1μF  
CC  
0.1μF  
0.1μF  
V
V
CC  
CC  
μC  
1
12  
1.7k  
1.7k  
REFOUT  
V
1k  
CC  
5
4
7
5
9
+
+
SCK/SCL  
MOSI/SDA  
MISO/SDO  
SCL  
IN  
IN  
LTC2473  
0.1μF  
1k  
6
3
SDA  
A0  
IN  
IN  
10  
GND  
8
COMP REF GND  
0.1μF  
0.1μF  
2
8
7, 11, 4  
0.1μF  
24713 TA02  
RELATED PARTS  
PART NUMBER  
DESCRIPTION  
COMMENTS  
LTC1860/LTC1861  
12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP  
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages  
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages  
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages  
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages  
3V Supply, 1.5mW at 100ksps, TSOT 6-pin/8-pin Packages  
LTC1860L/LTC1861L 12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC  
LTC1864/LTC1865 16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP  
LTC1864L/LTC1865L 16-bit, 3V, 1-/2-Channel 150ksps SAR ADC  
LTC2360  
LTC2440  
LTC2480  
12-Bit, 100ksps SAR ADC  
24-Bit No Latency Δ∑ADC  
200nV  
Noise, 4kHz Output Rate, 15ppm INL  
RMS  
16-Bit, Differential Input, No Latency Δ∑ ADC, with PGA,  
Temp. Sensor, SPI  
Easy-Drive Input Current Cancellation, 600nV  
Tiny 10-Lead DFN Package  
Noise,  
Noise,  
Noise,  
Noise,  
Noise,  
Noise,  
RMS  
RMS  
RMS  
RMS  
RMS  
RMS  
LTC2481  
LTC2482  
LTC2483  
LTC2484  
LTC2485  
16-Bit, Differential Input, No Latency Δ∑ ADC, with PGA,  
Easy-Drive Input Current Cancellation, 600nV  
Tiny 10-Lead DFN Package  
2
Temp. Sensor, I C  
16-Bit, Differential Input, No Latency Δ∑ ADC, SPI  
Easy-Drive Input Current Cancellation, 600nV  
Tiny 10-Lead DFN Package  
2
16-Bit, Differential Input, No Latency Δ∑ ADC, I C  
Easy-Drive Input Current Cancellation, 600nV  
Tiny 10-Lead DFN Package  
24-Bit, Differential Input, No Latency Δ∑ ADC, SPI with  
Temp. Sensor  
Easy-Drive Input Current Cancellation, 600nV  
Tiny 10-Lead DFN Package  
2
24-Bit, Differential Input, No Latency Δ∑ ADC, I C with  
Easy-Drive Input Current Cancellation, 600nV  
Tiny 10-Lead DFN Package  
Temp. Sensor  
LTC6241  
LTC2450  
Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp  
550nV Noise, 125μV Offset Max  
P-P  
Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V Input  
Range  
2 LSB INL, 50nA Sleep current, Tiny 2mm × 2mm DFN-6 Package,  
30Hz Output Rate  
LTC2450-1  
LTC2451  
LTC2452  
LTC2453  
Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V Input  
Range  
2 LSB INL, 50nA Sleep Current, Tiny 2mm × 2mm DFN-6 Package,  
60Hz Output Rate  
2
Easy-to-Use, Ultra-Tiny 16-Bit ADC, I C, 0V to 5.5V Input  
2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT  
Package, Programmable 30Hz/60Hz Output Rates  
Range  
Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, SPI, 5.5V  
Input Range  
2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT  
Package  
2
Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, I C, 5.5V  
2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT  
Package  
Input Range  
LTC2460  
LTC2462  
Ultra-Tiny 16-Bit Δ∑ ADC with 10ppm Reference  
Ultra-Tiny 16-Bit Δ∑ ADC with 10ppm Reference  
Pin and Software Compatible with LTC2471, 60Hz Output Rate  
Pin and Software Compatible with LTC2473, 60Hz Output Rate  
No Latency Δ∑ is a trademark of Linear Technology Corporation.  
24713f  
LT 0110 • PRINTED IN USA  
LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
20  
© LINEAR TECHNOLOGY CORPORATION 2010  
(408) 432-1900 FAX: (408) 434-0507 www.linear.com  
配单直通车
LTC2471IMS#TRPBF产品参数
型号:LTC2471IMS#TRPBF
Brand Name:Analog Devices Inc
是否无铅: 含铅
是否Rohs认证: 符合
生命周期:Active
包装说明:TSSOP,
针数:12
制造商包装代码:05-08-1668
Reach Compliance Code:compliant
风险等级:5.16
最大模拟输入电压:1.253 V
最小模拟输入电压:
最长转换时间:4800 µs
转换器类型:ADC, DELTA-SIGMA
JESD-30 代码:R-PDSO-G12
JESD-609代码:e3
长度:4.039 mm
最大线性误差 (EL):0.0183%
湿度敏感等级:1
模拟输入通道数量:1
位数:16
功能数量:1
端子数量:12
最高工作温度:85 °C
最低工作温度:-40 °C
输出位码:BINARY
输出格式:SERIAL
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260
认证状态:Not Qualified
座面最大高度:1.1 mm
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mm
Base Number Matches:1
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