Concurrent error detection revisited: hardware protection against fault and side-channel attacks
ARES '20: Proceedings of the 15th International Conference on Availability, Reliability and Security
Article No.: 20, Pages 1 - 11
Abstract
Fault Injection Analysis (FIA) and Side-Channel Analysis (SCA) are considered among the most serious threats to cryptographic implementations and require dedicated countermeasures to ensure protection through the entire life-cycle of the implementations.
In this work, our contribution is twofold. First, we present a novel orthogonal layout of linear Error-Correcting Codes (ECCs) to adjust classical Concurrent Error Detection (CED) to an adversary model that assumes precisely induced single-bit faults which, with a certain non-negligible probability, will affect adjacent bits. Second, we combine our orthogonal error correction technique with a state-of-the-art SCA protection mechanism to demonstrate resistance against both threats.
Eventually, using AES as a case study, our approach can correct entirely faulted bytes while it does not exhibit detectable first-order side-channel leakage using 200 million power traces and Test Vector Leakage Assessment (TVLA) as state-of-the-art leakage assessment methodology. Furthermore, our hardware implementations reduce the area and resource consumption by 14.9% -- 18.3% for recent technology nodes (compared to a conventional CED scheme).
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Index Terms
- Concurrent error detection revisited: hardware protection against fault and side-channel attacks
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Published: 25 August 2020
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- Bundesministerium für Bildung und Forschung
- Deutsche Forschungsgemeinschaft
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ARES 2020
ARES 2020: The 15th International Conference on Availability, Reliability and Security
August 25 - 28, 2020
Virtual Event, Ireland
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