demonstration

FPGA real time synthesis of simplified SIFT algorithm

Authors:

P. Rubio-Ibañez,

J. J. Martinez-Alvarez,

G. Domenech-AsensiAuthors Info & Claims

ICDSC '18: Proceedings of the 12th International Conference on Distributed Smart Cameras

Article No.: 26, Pages 1 - 2

https://doi.org/10.1145/3243394.3243706

Published: 03 September 2018 Publication History

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Abstract

This work presents an all-hardware real time implementation of the SIFT algorithm. The implementation exploits pipeline structures both in the keypoint extraction and in the descriptor generation stages to achieve real time requirements. To allow a feasible hardware implementations, some simplifications to the original algorithm have been required. The architecture has been synthesized on a Xilinx FPGA. It generates 3072 descriptor vectors for VGA images at 99 frames per second.

References

[1]

D. Lowe, "Distintive image features from scale-invariant keypoints," Int. J. Compt. Vis., vol. 60, no. 2, pp 91--110, Nov. 2004.

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[2]

L. Yao, et al, "An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcher" Proc. of the Intl. Conf. on Field-Programmable Technology, 30--37, 2009.

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[3]

M. Qasaimeh, et al, "FPGA-Based Parallel Hardware Architecture for Real-Time Image Classification", IEEE Trans. on Computational Imaging 1, 56--70, 2015.

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[4]

F. C. Huang et al, "High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction", IEEE Trans. on Circ. and Syst Video Tech. 22, 340--351, 2012.

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[5]

K. Mizuno, et al, "Fast and low-memory-bandwidth architecture of SIFT descriptor generation with scalability on speed and accuracy for VGA video", Proc. Intl. Conf. on Field Programmable Logic and Appl., 608--611, 2010.

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[6]

W. Deng et al, "An efficient hardware architecture of the optimised SIFT descriptor generation", Proc Proceedings of the Intl. Conf. on Field Programmable Logic and Applications, 345--352 (2012)

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[7]

G Domenech-Asensi et al, "All-hardware SIFT implementation for real-time VGA images feature extraction", J Real-Time Image Proc., 2018.

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Index Terms

FPGA real time synthesis of simplified SIFT algorithm
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Sensor devices and platforms

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Information & Contributors

Information

Published In

ICDSC '18: Proceedings of the 12th International Conference on Distributed Smart Cameras

September 2018

134 pages

ISBN:9781450365116

DOI:10.1145/3243394

General Chairs:
Lukas Esterle,
Andrea Prati,
Program Chairs:
Senem Velipasalar,
Victor Brea,
Caifeng Shan

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 September 2018

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Demonstration
Research
Refereed limited

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ICDSC '18

ICDSC '18: International Conference on Distributed Smart Cameras

September 3 - 4, 2018

Eindhoven, Netherlands

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Overall Acceptance Rate 92 of 117 submissions, 79%

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