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A CMOS Low Power 4th-Order Delta-Sigma Modulator with One Reconfigurable Amplifier

Published: 30 May 2018 Publication History

Abstract

This paper describes the 4th-order feedback delta-sigma modulator with only one reconfigurable amplifier. The modulator is designed with 180nm CMOS standard process. The measurement results demonstrate the power dissipation of 352uW, peak SNDR of 82.41dB and the ENOB of 13.4bits with an input signal frequency of 250Hz, a sampling frequency of 128 kHz, an input signal bandwidth of 1kHz, and an oversampling rate of 64.

References

[1]
S. H. Yang, J. H. Choi and G. S. Yoon, "A Design of Reconfigurable 4th Order delta-sigma Modulator Using Two Op-amps," Journal of The Institute of Electronics and Information Engineers, vol. 52, No. 5, pp. 875--881, May. 2015.
[2]
Y. Chae and G. Han, "Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator," IEEE J. Solid-State circuits, vol. 44, no. 2, pp. 458--472, Feb. 2009.
[3]
J. Choi and K. Yoon, "A CMOS Third Order ΔΣ Modulator with Inverter-Based Integrators," IEEE System on a chip Conference, September 2017.
[4]
A.P.Perez, E. Bonzzoni, and F. Maloberti, "A 88-dB DR, 84-dB SNDR very low-power single op-amp third-order ΣΔ modulator," IEEE Journal of Solid-State Circuits, Vol. 47, No. 9, pp. 2017--2118, Sep. 2012.
[5]
A.Pugliese; F.A.Amoroso; G.Cappuccino; G.Cocorullo, "Analysis of op-amp phase margin on SC delta-sigma modulator performances," Microelectronics Journal. Vol. 41. No. 7, pp. 440--446, July. 2010.
[6]
Ali Agah; Katelijin Vleugels; Peter B.Griffin, Mostafa Ronaghi; James D.Plummer; Bruce A. Wooley, "A High-Resolution Low-Power Incremental sigma-delta ADC With Extended Range for Biosensor Arrays", IEEE Journal of Solid-State Circuits, vol.45, no.6, pp. 1099--1110, June. 2010.
[7]
F.Michel and M.S.J.Steyaert, "A 250mV 7.5uW 61dB SNDR SC delta-sigma modulator using near-threshold-voltage-biased inverter amplifiers in 130nm CMOS," IEEE Journal of Solid-State Circuits, vol. 47, no. 3, pp. 709--721, Mar. 2012.
[8]
Yamamoto, K. and Carusone, A.C. "A 1--1-1--1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs," IEEE Journal of Solid-State Circuits, vol. 47, no. 1, pp. 1866--1883, Aug. 2012.
[9]
A. Ismail and I. Mostafa, "A Process-Tolerant, Low-Voltage, Inverter-Based OTA for Continuous-Time Delta-Sigma ADC", IEEE Transactions on Very Large Scale Integration Systems, vol. 24, pp. 2911--2917, 2016.
[10]
S. Richards and G. C. Temes, Understanding Delta Sigma data converters, Wiley Interscience, 2005
[11]
S. Richards and J. Silva and J. Streensgaard and G. C. Temes, "Design-Oriented Estimation of Thermal Noise in Switched-Capacitor Circuits," IEEE Transactions On Circuits And Systems. Vol. 52m No. 11, pp. 2358--2368,Nov.2005.

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    cover image ACM Conferences
    GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI
    May 2018
    533 pages
    ISBN:9781450357241
    DOI:10.1145/3194554
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 30 May 2018

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    Author Tags

    1. CMOS
    2. delta-sigma modulator
    3. low power
    4. reconfigurable amplifier

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    • Research-article

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    • Ministry of Education

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    GLSVLSI '18
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    GLSVLSI '18: Great Lakes Symposium on VLSI 2018
    May 23 - 25, 2018
    IL, Chicago, USA

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    GLSVLSI '18 Paper Acceptance Rate 48 of 197 submissions, 24%;
    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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